Segmented Source/Drain Contacts for Stable Low-Pitch 3D Transistors
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Solution Overview
Problem
There is a need to reduce capacitance between contacts in semiconductor devices while ensuring electrical stability as pitch size decreases, particularly in multi gate transistors with three-dimensional channels, to improve scaling and current control capability.
Innovation Solution
The semiconductor device incorporates a lower interlayer insulating layer with active patterns, a gate structure, source/drain patterns, and conductive layers, featuring contact separation patterns and insulating liners to manage capacitance and enhance electrical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size is reduced to increase device density, then device density is improved, but capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The contact structure is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) separated by insulating layers. This segmentation reduces capacitance between adjacent contacts while maintaining electrical stability, allowing pitch size reduction without compromising reliability
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first conductive layer and the second conductive layer. This intermediary reduces the capacitance between contacts formed in different conductive layers, enabling higher device density while maintaining electrical stability
2Object-affected harmful factors
If contact separation is increased to reduce capacitance, then capacitance is reduced, but device area increases
Solution Approach 1:
The contact separation problem is solved by transitioning from a two-dimensional planar separation to a three-dimensional vertical stacking approach. Multiple conductive layers are stacked vertically with insulating layers in between, reducing capacitance through vertical separation rather than horizontal spacing, thus maintaining compact device area
3Reliability
If multi gate transistor with three-dimensional channel is implemented to improve scaling and current control, then current control capability is improved, but device complexity increases
Solution Approach 1:
The gate structure is designed to wrap around the active pattern, providing multi-functional control over the three-dimensional channel. This wrap-around configuration enables effective current control and scaling while maintaining a relatively simple fabrication process through standardized semiconductor manufacturing techniques
Data Source
AI summary
A semiconductor device includes a lower interlayer insulating layer including a first surface and a second surface that are opposite to each other in a first direction; a plurality of active patterns disposed on the first surface of the lower interlayer insulating layer; a gate structure disposed on the first surface of the lower interlayer insulating layer; a source/drain pattern connected to the plurality of active patterns; a lower conductive layer that is disposed on the second surface of the lower interlayer insulating layer and includes a first surface and a second surface; a lower source/drain contact protruding from the lower conductive layer in the first direction and connected to the source/drain pattern; and a contact separation pattern that penetrates the lower conductive layer and is in contact with the lower interlayer insulating layer.