Segmented Control Gate Lines for Semiconductor Memory Reliability
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Solution Overview
Problem
The increasing miniaturization of semiconductor memory devices leads to closer distances between elements like bit lines, word lines, control gate lines, and erase gate lines, which can induce defects and affect efficiency due to finer layouts and higher chances of short circuits.
Innovation Solution
The implementation of segmented control gate lines with protrusions and strategically placed spacings between segments, along with segmented word lines, to reduce trench aspect ratios and prevent defects, while maintaining the same layout size without increasing inter-element distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sizes of semiconductor memory devices become smaller and elements are formed finer and closer, then the integration capability and memory capacity are improved, but defects such as residues and short circuits are induced and device reliability deteriorates
Solution Approach 1:
The control gate lines are divided into multiple segments with spacings between them, breaking the continuous structure into discrete parts. This segmentation reduces the trench aspect ratio and prevents defect formation while maintaining the overall functionality of the control gate, thus resolving the contradiction between integration density and device reliability
Solution Approach 2:
The invention introduces spacings at specific locations between control gate line segments where defects are most likely to occur. By applying the spacing structure locally at critical positions rather than uniformly throughout, the design maintains high integration capability while preventing defects at vulnerable points, improving device reliability without sacrificing productivity
2Area of stationary object
If control gate lines are formed closer together to increase integration, then the layout density is improved, but the trench aspect ratio increases and defects are induced
Solution Approach 1:
By segmenting the control gate lines and introducing spacings between segments, the effective trench depth is reduced while maintaining the horizontal spacing between adjacent control gate lines. This allows high layout density to be achieved without excessive trench aspect ratios, preventing manufacturing defects
Solution Approach 2:
The invention addresses the trench aspect ratio problem by introducing spacings in the vertical dimension (between control gate line segments) rather than increasing horizontal spacing. This dimensional approach maintains layout density while reducing the effective trench depth, improving manufacturing precision
3Reliability
If spacings are introduced between control gate line segments, then defects are reduced and reliability is improved, but the layout area increases
Solution Approach 1:
Spacings are introduced only at specific critical locations between control gate line segments where defect formation is most likely, rather than uniformly across the entire layout. This localized approach improves device reliability by preventing defects at vulnerable points while minimizing the additional layout area required
Data Source
AI summary
A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.