Segmented Monotonic Counter for Low-Write NVM Increments
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Solution Overview
Problem
Existing monotonic counter implementations face inefficiencies in incrementing operations, leading to increased power consumption and reduced endurance due to the need for multiple write and erase operations in single memory cell increments.
Innovation Solution
The proposed solution involves a monotonic counter design that stores its value in N binary words across N memory cells of a non-volatile memory, where incrementing operations erase a memory cell and write the incremented value in a subsequent cell, reducing the number of elementary operations by half, thereby minimizing power consumption and enhancing endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional monotonic counter incrementing operations are implemented in single memory cell, then counter value can be updated, but multiple write and erase operations are required leading to increased power consumption and reduced endurance
Solution Approach 1:
The counter value is segmented into N binary words stored in N memory cells of non-volatile memory, where each cell stores a portion of the overall counter value. This segmentation allows the incrementing operation to be distributed across multiple cells, reducing the number of write and erase operations required in any single cell and thereby improving endurance while maintaining functionality.
2Productivity
If traditional monotonic counter incrementing operations are implemented in single memory cell, then counter value can be updated, but multiple write and erase operations increase the number of elementary operations
Solution Approach 1:
The counter is divided into N segments (binary words) stored in N memory cells. The incrementing operation processes these segments in a coordinated manner, reducing the total number of elementary write and erase operations by distributing the operation across the segmented structure rather than repeatedly modifying a single cell.
Solution Approach 2:
The solution transitions from a single-dimension approach (one memory cell) to a multi-dimensional approach (N memory cells arranged in a modular structure with consecutive ranks). This dimensional expansion allows the system to perform incrementing operations more efficiently by utilizing the spatial arrangement and modular architecture of the N-cell structure.
Data Source
AI summary
A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N−3.