Segmented DAC Architecture for High-Accuracy Conversion in Less Area
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Solution Overview
Problem
High-accuracy digital-to-analog converter (DAC) circuits require significant circuit area and increased bit accuracy leads to more switches, resistor elements, calibration memory, and time, making them inefficient in terms of space and power consumption.
Innovation Solution
The development of segmented DAC circuits that include a resistor DAC for the most significant bit, an interpolation DAC for offsetting, and a Sigma Delta modulator for digital interpolation, along with a calibration method to measure and calculate calibration codes for efficient DAC operation, reducing the number of switches and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but circuit area and power consumption increase significantly
Solution Approach 1:
The DAC is divided into multiple segments: an MSB DAC handling the most significant bits and an interpolation DAC handling the less significant bits. This segmentation allows each sub-DAC to use fewer circuit elements while collectively achieving high-resolution conversion, thereby reducing the total circuit area compared to a single high-resolution DAC.
Solution Approach 2:
A Sigma-Delta modulator is introduced as an intermediary between the digital input and the interpolation DAC. It converts the less significant bits into a high-frequency signal that the interpolation DAC can process with fewer elements, effectively mediating the trade-off between resolution and circuit complexity.
2Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but the number of switches and resistor elements increases
Solution Approach 1:
The DAC architecture segments the conversion task into two parts: the MSB DAC uses a simplified structure with fewer switches and resistors for the most significant bits, while the interpolation DAC handles the remaining bits with even fewer elements. The overall complexity is reduced because each segment uses only the minimum necessary elements for its resolution requirement.
Solution Approach 2:
The patent replaces traditional resistive switching mechanisms with a combination of pulse-density modulation and current-mode interpolation. This substitution reduces the number of physical switches and resistor elements by using temporal modulation and current steering instead of complex resistive networks.
3Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but calibration time and memory requirements increase
Solution Approach 1:
The calibration process is segmented into two independent parts: calibration of the MSB DAC and calibration of the interpolation DAC. Each sub-DAC can be calibrated separately with fewer test points and less time, rather than calibrating the entire high-resolution DAC as a single unit. This reduces total calibration time while maintaining overall accuracy.
Solution Approach 2:
The MSB DAC is calibrated first, and its calibration results are stored and used as a reference for the subsequent interpolation DAC calibration. This preliminary action allows the second calibration to focus only on the interpolation errors, reducing the overall calibration complexity and time required.
Data Source
AI summary
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.