Segmented Non-Binary DAC Calibration Using ADC Feedback
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Solution Overview
Problem
High precision digital to analog converters (DACs) face challenges in achieving linearity, especially at accuracy levels of 18 bits or greater, due to voltage coefficients in resistor-based DAC architectures.
Innovation Solution
A self-calibrating method for a segmented non-binary DAC system, which involves providing cumulative and non-cumulative series of calibration input digital signals, measuring corresponding outputs, calculating scaling factors, and storing them for application during normal operation to improve linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high accuracy analog trimming procedures are used to improve DAC linearity, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The DAC system performs self-calibration by using its own output to generate calibration data. The system applies test digital input codes, measures the analog output with an ADC, and automatically calculates correction factors without requiring external trimming equipment or manual adjustment procedures.
Solution Approach 2:
The calibration process is performed in advance during manufacturing or system initialization. Correction factors are pre-calculated and stored in memory before the DAC enters normal operation, eliminating the need for complex real-time trimming procedures during manufacturing.
2Manufacturing precision
If resistor-based DAC architecture is used to achieve high precision, then manufacturing precision is improved, but non-linearity increases due to voltage coefficients
Solution Approach 1:
The system uses feedback by measuring the actual analog output with an ADC and comparing it to the expected output. Based on this feedback, correction factors are calculated to compensate for the non-linear voltage coefficients of the resistors, and these corrections are applied to subsequent digital input codes.
Solution Approach 2:
The system changes the digital input codes by applying correction factors to compensate for the non-linear characteristics of the resistor-based architecture. This parameter transformation allows the DAC to achieve high precision despite the inherent non-linearity of the physical components.
3Manufacturing precision
If calibration procedures are implemented to reduce non-linearity, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The calibration process is automated and performed by the DAC system itself using standard test equipment. The system generates its own calibration data by applying test codes and measuring outputs, eliminating the need for complex external calibration equipment or skilled manual adjustment procedures.
Solution Approach 2:
All calibration activities are performed in advance during manufacturing or system initialization. The correction factors are pre-calculated and stored in memory, so no complex calibration procedures are needed during field installation or maintenance, greatly simplifying the manufacturing and deployment process.
Data Source
AI summary
The disclosure relates to self-calibration of non-linearity in a digital to analog converter (DAC). Example embodiments include a method for calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the method comprising: providing first calibration input digital signals to a thermometric weighted segment and measuring first outputs of the DAC with an ADC; providing second calibration input digital signals to the thermometric weighted segment and measuring second outputs of the DAC with the ADC; calculating a first scaling factor for first switches and resistive elements by dividing each of the second outputs of the DAC by a difference between adjacent ones of the first outputs of the DAC; calculating a second scaling factor for second switches from a sum of the first outputs of the DAC divided by a measured output range of the DAC; and storing the first and second scaling factors in a memory module.