Segmented DAC-ADC Loopback Testing for Dynamic Harmonic Prediction

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Solution Overview

Problem

Conventional loopback testing methods for on-chip segmented digital-to-analog converters (DAC) and analog-to-digital converters (ADC) face challenges in accurately predicting dynamic nonlinearities, leading to fault masking and high production costs due to the high cost of automated-test equipment and lengthy test times.

Innovation Solution

A loopback-based self-test technique using an external load board with parallel programmable-gain-amplifier (PGA) and bypass paths to predict dynamic nonlinearities of on-chip segmented DAC and ADC by performing two loopback tests and processing simultaneous equations to obtain harmonic coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional loopback testing is used for on-chip segmented DAC and ADC, then test implementation is simple, but fault masking occurs and dynamic nonlinearities cannot be accurately predicted

Engineering Contradiction:

Improvetest implementation simplicityVSAvoiddynamic nonlinearity prediction accuracy

Core Design Contradiction:

Ease of operationVSMeasurement precision

Solution Approach 1:

The patent divides the segmented DAC and ADC into coarse and fine sub-converters, testing each separately through selective activation. By isolating sub-converters and testing them individually, the method eliminates mutual fault masking while maintaining the simplicity of loopback testing architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a programmable gain amplifier (PGA) as an intermediary component in the test signal path. The PGA enables flexible signal routing and gain adjustment, allowing separate characterization of coarse and fine sub-converters without requiring complex external test equipment.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional loopback testing with two DUT channels is used, then test cost is reduced, but mutual fault masking leads to product yield loss

Engineering Contradiction:

Improvetest costVSAvoidproduct yield

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the testing process into separate tests for coarse and fine sub-converters. By activating only one sub-converter at a time and routing its output through the PGA to the appropriate ADC input, the method enables independent characterization of each segment, eliminating the fault masking problem that reduces product yield.

Inventive Principle:

Principle #1Segmentation

3Reliability

If separate testing of coarse and fine sub-converters is implemented, then fault masking is eliminated, but test complexity increases

Engineering Contradiction:

Improvefault detection accuracyVSAvoidtest configuration complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the PGA serve multiple functions: signal routing, gain adjustment, and enabling separate characterization of different sub-converters. This multi-functional approach allows complex separate testing to be achieved without proportionally increasing hardware complexity, as the single PGA handles all test signal conditioning needs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Measurement precision

If traditional ATE is used for segmented data converter testing, then comprehensive testing is achieved, but test cost and test time increase significantly

Engineering Contradiction:

Improvetesting comprehensivenessVSAvoidtest cost and test time

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent enables the DUT to test itself by using its own functional blocks (coarse DAC, fine DAC, coarse ADC, fine ADC) in a loopback configuration. The PGA routes signals internally, allowing the device to characterize its own sub-converters without external test equipment, dramatically reducing both test cost and test time while maintaining comprehensive testing capability.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11296715B1Built-in harmonic prediction method for embedded segmented-data-converters and system thereof

Publication Date: 2022.04.05 IND -UNIV CORP FOUNDATION HANYANG UNIV ERICA CAMPUS

AI summary

The inventive concept relates to a method and system for cost-effectively predicting the dynamic nonlinearities of on-chip segmented digital-to-analog converter (DAC) and analog-to-digital-converter (ADC), by looping a DAC to an ADC, using a programmable-gain-amplifier (PGA) and an external load board. The method may include a first loopback step of supplying an output signal from a coarse DAC, to which a sinusoidal signal is supplied, to a coarse ADC and a fine ADC through an external load board, a second loopback step of supplying an output signal from a fine DAC, to which a sinusoidal signal is supplied, to the fine ADC and the coarse ADC through the load board, and a step of predicting dynamic nonlinearity of each of a DAC and an ADC by processing equations exhibiting dynamic nonlinearity of a sub-DAC and a sub-ADC, which are obtained in the first loopback step and the second loopback step.