Segmented DAC Architecture for High Accuracy in Less Circuit Area
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Solution Overview
Problem
High-accuracy digital-to-analog converter (DAC) circuits require significant circuit area and increased calibration memory and time due to the need for numerous switches and resistor elements, which complicates their integration into microcontrollers and microprocessor circuits for applications like medical devices and industrial control.
Innovation Solution
The development of segmented DAC circuits that include a resistor DAC for the most significant bit, an interpolation DAC for offsetting, and a Sigma Delta modulator for digital interpolation, along with a calibration method that measures and calculates output voltages to generate calibration codes, reducing the number of switches and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent divides the DAC circuit into three independent segments: an M-bit resistor DAC for the most significant bit, an I-bit interpolation DAC for the intermediate bit, and an L-bit Sigma Delta modulator for the least significant bit. Each segment processes a different portion of the digital input signal, allowing the circuit to achieve high accuracy without requiring a single large-scale DAC structure, thus reducing overall circuit area while maintaining conversion precision.
2Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but calibration memory and calibration time increase
Solution Approach 1:
The calibration process is segmented into three independent calibration procedures, one for each DAC segment (resistor DAC, interpolation DAC, and Sigma Delta modulator). Each segment is calibrated separately using its own calibration codes stored in dedicated calibration memory. This segmentation allows the total calibration memory requirement to be distributed across smaller portions rather than requiring a single large calibration memory, reducing the overall quantity of calibration data needed while maintaining high accuracy.
3Measurement precision
If the number of switches and resistor elements is increased, then DAC accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the DAC functionality into three distinct circuits, each with its own optimized component set. The resistor DAC uses a compact resistor network for MSB conversion, the interpolation DAC uses a separate resistor network for intermediate bits, and the Sigma Delta modulator uses minimal components for LSB processing. This segmentation allows each segment to use fewer components optimized for its specific function, reducing the total number of switches and resistor elements compared to a single monolithic high-accuracy DAC while maintaining overall accuracy.
4Measurement precision
If traditional DAC circuits are used, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The segmented architecture allows each DAC segment to operate independently with optimized power characteristics. The resistor DAC, interpolation DAC, and Sigma Delta modulator can be powered at different voltage levels and with different switching frequencies tailored to their specific requirements. This segmentation enables more efficient power distribution and reduces overall power consumption compared to a single high-accuracy DAC circuit that would require uniform high-power operation across all components.
Data Source
AI summary
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.