Segmented DAC Current Weighting for High-Resolution Linearity

The patent divides the high-resolution DAC into multiple lower-resolution sub-DACs, each handling a portion of the input bits. For example, a 12-bit DAC is segmented into multiple 6-bit sub-DACs, where each sub-DAC uses fewer resistors (2^6 = 64 resistors per sub-DAC vs. 2^12 = 4096 resistors for a full 12-bit DAC). The outputs of these sub-DACs are then combined through weighted summation to achieve the full resolution, thereby reducing the area and parasitic capacitance while maintaining output precision.

The patent segments the switch array into multiple smaller switch arrays, each associated with a sub-DAC. Each sub-DAC requires only 2^(N/k) switches instead of 2^N switches for the full resolution, significantly reducing the total parasitic capacitance. The segmented switch arrays control the segmented resistor strings in each sub-DAC, and their combined outputs achieve the full resolution with much lower parasitic capacitance.

The patent extracts and eliminates the buffer component from the coupling mechanism between fine and coarse strings. Instead of using buffers to couple the segmented sub-DAC outputs, the invention directly combines the outputs through a summation network that weights each sub-DAC output according to its significance. This removes the buffer offset error source while maintaining proper loading conditions through the weighted combination architecture.

The patent replaces the complex current sources with simpler resistive elements and passive combining networks. Instead of requiring precisely matched current sources for each segment, the invention uses segmented resistor strings with weighted combinations where the weighting is achieved through simple resistor ratios or switch configurations. This approach achieves the loading elimination effect through the segmented architecture itself rather than through active current sources, significantly reducing implementation complexity.