Segmented DAC Circuit With Fewer Switches and Smaller Layout
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Solution Overview
Problem
Conventional digital to analog converters require a large number of switches, leading to significant layout area occupation in mixed-mode systems, which is inefficient and costly.
Innovation Solution
A digital to analog converter design that generates (2n+1) reference voltages and uses a switch array with fewer switches than conventional designs, where the first output terminal outputs odd reference voltages and the second output terminal outputs even reference voltages, controlled by an n-bit input signal, reducing the number of switches required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional digital to analog converter uses N×2^N+2^N switches for implementation, then the conversion function is achieved, but the layout area becomes large
Solution Approach 1:
The patent segments the conventional single-stage DAC architecture into two cascaded stages: a first-stage DAC with (N-2) bits and a second-stage DAC with 2 bits. This segmentation reduces the switch count in each stage, with the first stage requiring (N-2)×2^(N-2)+(N-2) switches and the second stage requiring only 4 switches, totaling fewer switches than the conventional single-stage design
Solution Approach 2:
The patent introduces a new architectural dimension by cascading two DAC stages instead of using a single stage. The first stage processes MSB (most significant bits) and the second stage processes LSB (least significant bits), creating a hierarchical structure that reduces overall complexity and switch count while maintaining conversion accuracy
Data Source
AI summary
A digital to analog converter with two outputs controlled by an input signal with n-bits is disclosed. A reference voltage circuit generates (2n+1) reference voltages numbered from 1 to (2n+1). A switch array coupled to the reference voltage circuit, a first output terminal, and a second output terminal, includes a plurality of switches switching according to the input signal. The first output terminal outputs only one of odd reference voltages according to the input signal, and the second output terminal outputs one of even reference voltages according to the input signal, and the number of the switches is less than (n×2n+2n).