Segmented Resistor Ladder DAC Blanking for Glitch Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Segmented resistor ladder digital-to-analog converters (DACs) experience high voltage glitches during transitions between binary weighted and thermometer encoded segments, which complicates area-efficient implementation, especially at high resolutions.

Innovation Solution

A blanking circuit is introduced that uses a transmission gate controlled by selected bits of the binary-encoded digital input signal to block voltage glitches, either during specific transitions or all transitions, by pulsing the gate off when the selected bits change, thereby reducing glitches in the analog output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a segmented DAC combining binary weighted and thermometer encoded segments is used for area optimization, then area efficiency is improved, but voltage glitches occur during transitions between segments

Engineering Contradiction:
ImproveDAC areaVSAvoidvoltage glitches
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

A transmission gate is introduced as an intermediary component between the segmented DAC output and the external circuit. This gate is controlled by a blanking signal generated from selected bits of the digital input, allowing it to block voltage glitches during segment transitions while passing valid output signals during normal operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The blanking circuit generates a blanking signal in advance based on selected bits of the digital input signal. This signal proactively disables the transmission gate before voltage glitches can propagate to the output, preventing harmful effects before they occur.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If high resolution greater than six bits is desired, then precision is improved, but a pure thermometer-encoded resistor ladder cannot be implemented due to area constraints

Engineering Contradiction:
ImproveDAC resolutionVSAvoidDAC area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The DAC is divided into multiple segments: a binary weighted segment and a thermometer encoded segment. The binary weighted segment handles the most significant bits requiring fewer components, while the thermometer segment handles the least significant bits requiring high precision. This segmentation enables high-resolution DAC implementation in a compact area.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the transmission gate is blanked during transitions to eliminate glitches, then signal integrity is improved, but transmission time is increased during blanking periods

Engineering Contradiction:
Improvesignal integrityVSAvoidtransmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The transmission gate operates in periodic cycles: enabled during normal signal transmission and disabled during transition periods. The blanking signal creates periodic blanking intervals that coincide with digital input transitions, blocking glitches only when necessary while maintaining continuous signal transmission during stable periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10826515B2Glitch reduction in segmented resistor ladder DAC
Publication Date: 2020.11.03 TEXAS INSTRUMENTS INC
  • US10826515B2 patent drawing
  • US10826515B2 patent drawing
  • US10826515B2 patent drawing

AI summary

An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.