Segmented Resistive DAC Layout for Accuracy and Monotonicity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in achieving efficient layout area while maintaining accuracy and monotonicity, particularly due to the large area consumption of resistors with the same resistance, which affects their implementation on system-on-chip (SoC) devices.
Innovation Solution
The proposed solution involves a segmented Resistive DAC (R-DAC) design with multiple sub-DACs and binary-to-thermometer decoders, where resistors in the first and third sub-DACs have lower resistance than those in the second sub-DAC, allowing for reduced area consumption while maintaining accuracy and monotonicity by using switches to connect resistors to high or low reference voltages based on thermometer code bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If resistors with the same resistance are used in all sub-DACs, then accuracy and monotonicity are maintained, but the layout area increases significantly
Solution Approach 1:
The patent applies local quality by assigning different resistance values to resistors in different sub-DACs based on their specific functional requirements. The first sub-DAC uses resistors with first resistance values, the second sub-DAC uses resistors with second resistance values, and the third sub-DAC uses resistors with third resistance values. This localized differentiation allows each sub-DAC to be optimized for its specific role while maintaining overall system accuracy, thereby reducing the total layout area compared to using uniform resistance values throughout.
2Area of stationary object
If resistors with lower resistance are used, then area consumption is reduced, but resistor mismatch increases affecting monotonicity
Solution Approach 1:
The patent segments the DAC into multiple sub-DACs (first, second, and third sub-DACs) with different resistance values. By dividing the overall conversion function across these segments, each sub-DAC can use lower resistance values that consume less area, while the segmented architecture itself provides redundancy and control mechanisms that maintain monotonicity. The segmentation allows the system to achieve both area efficiency and reliability through distributed functionality.
Solution Approach 2:
The patent introduces scaling resistors as intermediary elements between sub-DACs to manage and balance the different resistance values. These scaling resistors act as mediators that ensure proper signal level transitions and maintain monotonicity across the segmented structure, even when individual sub-DACs use lower resistance values for area efficiency.
3Area of stationary object
If more sub-DACs with different resistance values are used, then area efficiency improves, but device complexity increases
Solution Approach 1:
The patent divides the DAC into three distinct sub-DACs with different resistance values optimized for their specific functions. This segmentation improves area efficiency by allowing each segment to use appropriately sized resistors rather than oversizing all resistors to accommodate the most demanding requirements. The segmentation is structured to manage complexity through functional separation while maintaining overall system coherence.
Solution Approach 2:
The patent systematically varies the resistance parameter across different sub-DACs (first resistance, second resistance, third resistance) to optimize area usage. By changing this key parameter in a controlled manner across segments, the design achieves area efficiency while the systematic approach to parameter variation helps manage device complexity through predictability and structured design.
Data Source
AI summary
A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.