Segmented Interpolation DAC for 16-Bit Accuracy With Less Calibration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DAC circuits for microcontrollers face challenges in achieving high accuracy (e.g., 16 bit resolution) due to significant circuit area occupation, increased number of switches and resistor elements, and lengthy calibration processes, which result in high costs and complexity.
Innovation Solution
A segmented DAC circuit utilizing an interpolation RDAC and a buffer amplifier is introduced, which includes a MSB R-2R DAC for coarse interpolation and an ISB resistor ladder for final interpolation, reducing the need for an interpolation amplifier and minimizing calibration memory and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC circuits use increased number of switches and resistor elements to achieve higher bit accuracy, then DAC accuracy is improved, but circuit area and device complexity increase significantly
Solution Approach 1:
The patent divides the DAC circuit into multiple segments or stages, where each stage handles a portion of the bit resolution. This segmentation allows the circuit to achieve high overall accuracy without requiring all switches and resistors to be simultaneously active, thereby reducing circuit complexity and area while maintaining high DAC accuracy through coordinated operation of segmented stages.
2Measurement precision
If conventional DAC circuits increase the number of switches and resistor elements for higher bit accuracy, then DAC accuracy is improved, but circuit area occupation increases
Solution Approach 1:
The patent employs dynamic switching mechanisms where switches and resistor elements are activated selectively based on the required resolution and input conditions. This dynamic operation allows the circuit to achieve high DAC accuracy when needed while minimizing circuit area occupation during lower-resolution operations, as not all circuit elements are simultaneously engaged.
3Measurement precision
If conventional DAC circuits provide high bit accuracy, then DAC accuracy is improved, but calibration memory and calibration time are increased
Solution Approach 1:
The patent segments the calibration process into multiple stages corresponding to different bit resolutions. This allows calibration to be performed incrementally rather than requiring complete calibration of all bits simultaneously, thereby reducing calibration time while maintaining high DAC accuracy. The segmented approach also reduces calibration memory requirements by calibrating only the necessary segments.
4Measurement precision
If conventional DAC circuits provide high bit accuracy, then DAC accuracy is improved, but more calibration memory is required
Solution Approach 1:
The patent divides calibration memory into segmented portions, where each segment stores calibration data for a specific portion of the DAC circuit or bit range. This segmentation reduces the total calibration memory required compared to storing complete calibration data for all bits, while still achieving high DAC accuracy through coordinated use of segmented calibration information.
Data Source
Figure 1~2
Figure 3
Figure 4A~4D
AI summary
A segmented digital-to-analog converter (DAC) 100 includes an interpolation resistor DAC (RDAC) 108 and a buffer amplifier 110. The interpolation RDAC 108 includes a resistor-two-resistor (R-2R) DAC 192 and a resistor ladder 194. The R-2R DAC 192 receives a first subword 126M and generates an analog output signal 136H-136L with a voltage representative of the first subword 126M. The first subword 126M has an integer number M bits that include a most significant bit (MSB) of a digital input signal 122. The resistor ladder 194 receives the analog output signal 136H-136L and a second subword 126I and generates an analog interpolated signal 146. The second subword 126I has an integer number I bits that include an intermediate significant bit (ISB) of the input signal 122. The buffer amplifier 110 receives the analog interpolated signal 146 and generates an output signal 124 for the segmented DAC 100.