Segmented DAC Level Shifting for Major Code Transition Glitch Reduction
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Solution Overview
Problem
Digital-to-analogue converters (DACs) configured with a main DAC and a sub-DAC experience significant voltage spikes, known as major code transition glitches, during changes in the most significant bits (MSBs), which disrupt closed-loop control applications and pulse width modulation, despite previous attempts to minimize these disturbances.
Innovation Solution
Incorporating a level shifting circuit that selectively alters the analogue output signal's voltage value and adjusts the least significant bits (LSBs) applied to the sub-DAC to compensate for voltage changes, thereby minimizing major code transition glitches by avoiding transitions between adjacent MSB codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the sub-DAC is moved from interpolating across one main impedance element to the next adjacent main impedance element during major code transitions, then the DAC can convert the full range of input codes, but a relatively large voltage spike develops in the analogue output voltage
Solution Approach 1:
The level shifting circuit proactively shifts the voltage level of the analogue output signal before the main DAC circuit transitions between adjacent MSB codes. By detecting when the sub-DAC is approaching a major code transition threshold, the circuit preemptively adjusts the voltage level, preventing the harmful voltage spike from occurring in the first place.
Solution Approach 2:
The level shifting circuit acts as an intermediary between the main DAC circuit and the output, mediating the voltage transitions. It introduces a compensating voltage shift that offsets the discontinuity that would otherwise occur during major code transitions, smoothing the output voltage waveform.
2Reliability
If the main DAC circuit transitions from one major code to the next major code, then the full dynamic range is covered, but major code transition glitches occur in the analogue output voltage
Solution Approach 1:
The control circuit continuously monitors the digital input code and detects when a major code transition is imminent. Based on this feedback, it activates the level shifting circuit at the appropriate moment to prevent the glitch, creating a closed-loop control system that maintains output stability.
Solution Approach 2:
The level shifting circuit dynamically changes the voltage parameter of the analogue output signal by a predetermined amount (at least one LSB) at critical transition points. This parameter modification prevents the instability that would otherwise occur during major code transitions.
3Object-generated harmful factors
If the level shifting circuit alters the voltage value of the analogue output signal, then major code transition glitches are minimized, but the voltage value of the output signal changes
Solution Approach 1:
The level shifting circuit introduces an intermediary voltage adjustment that compensates for the discontinuity during transitions. The control circuit calculates the appropriate shift amount to maintain the correct overall output voltage level while preventing glitches.
Solution Approach 2:
The DAC system combines two functional components: the main DAC circuit for full-range conversion and the level shifting circuit for glitch prevention. This composite architecture achieves both glitch minimization and voltage accuracy by coordinating the operation of both components.
Data Source
AI summary
An N-bit DAC comprises a main DAC circuit having main nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one MSB value, and a sub-DAC circuit having secondary nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one LSB. A main switch network couples the secondary nodes to a selected pair of main nodes as the MSB value of the digital input signal varies. A secondary switch network selectively couples one of secondary nodes to an output terminal for providing an analogue voltage output signal. The main nodes are coupled between main terminals, and a voltage reference is applied across input terminals. A first offset circuit and a first compensating circuit are selectively coupleable between the main DAC circuit and the input terminals for offsetting the main node analogue voltages downwardly.