Segmented Resistor-Array DAC for 12-Bit Linearity
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Solution Overview
Problem
Current digital-to-analog converters (DACs), particularly R-2R architectures, face limitations in achieving high accuracy beyond 8-10 bits due to binary scaling errors and high current consumption, which restricts their practical application in higher resolution applications like 12-bit DACs.
Innovation Solution
A DAC is subdivided into multiple sub-DACs, each with an array of resistors, and a scaling resistor is connected between adjacent sub-DACs to ensure each resistor branch is equally weighted, reducing power consumption and improving linearity by distributing error across multiple bits, thus achieving monotonic operation suitable for 12-bit resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If R-2R architecture is used, then current consumption is reduced compared to current steering DAC, but accuracy is limited to 8-10 bits due to binary scaling errors
Solution Approach 1:
The DAC is divided into multiple sub-DACs, each handling a specific portion of the digital input bits. This segmentation eliminates the need for binary scaling across the entire DAC, as each sub-DAC uses only unit resistors of value R, thereby removing the source of binary scaling errors while maintaining lower current consumption compared to full current steering architecture
Solution Approach 2:
Each sub-DAC is designed with uniform unit resistors of value R, creating local homogeneity within each sub-DAC. The binary scaling is eliminated locally in each sub-DAC segment, while the overall DAC achieves high accuracy through the combination of segmented sub-DACs with properly scaled output contributions
2Speed
If current steering DAC is used, then high speed is achieved, but current consumption surpasses allowable total current consumption
Solution Approach 1:
The current steering operation is segmented across multiple sub-DACs, each operating independently on its assigned bit portion. This allows each sub-DAC to use smaller, more manageable current levels while maintaining the high-speed switching characteristics of current steering architecture, thereby achieving allowable total current consumption without sacrificing conversion speed
3Device complexity
If binary scaling is applied at each stage, then R-2R DAC structure is maintained, but large errors are introduced limiting accuracy
Solution Approach 1:
The binary scaling function is extracted from each individual sub-DAC stage and replaced with simple resistor switching using only unit resistors of value R. The scaling effect is achieved externally through the weighted combination of sub-DAC outputs rather than through binary scaling within each stage, thereby eliminating the large errors associated with binary scaling while maintaining the R-2R structural benefits
Data Source
Figure 1~2
Figure 3
AI summary
A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.