Segmented DAC Circuit for Small-Signal Linearity Control
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Solution Overview
Problem
In communication systems, such as 5G, digital-to-analog converters (DACs) face challenges in maintaining linearity and dynamic range performance when converting small digital input sizes into analog outputs, due to errors in the conversion process.
Innovation Solution
The implementation of a DAC that includes a controller generating a control signal based on the digital input, and a segment cell circuit with multiple segment cells turned on or off according to the control signal. This circuit divides the digital input into bit groups, with additional segment cells used to reduce errors during state changes, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional DAC structure is used for small digital input sizes, then the device complexity remains low, but the linearity and dynamic range performance degrade due to conversion errors
Solution Approach 1:
The digital input bits are divided into multiple bit groups (first bit group, second bit group, third bit group), and corresponding segment cells are configured for each bit group. This segmentation allows the DAC to handle small digital input sizes more accurately by processing different bit groups through dedicated segment cells, thereby improving linearity and dynamic range performance without requiring a complete redesign of the entire DAC structure.
2Measurement precision
If additional segment cells are added to reduce conversion errors, then the linearity performance improves, but the device complexity increases
Solution Approach 1:
The additional segment cell is specifically configured to handle the lowermost bit of the second bit group, providing enhanced precision for this particular bit position. This local quality approach ensures that conversion accuracy is improved where it is most needed (for small digital input sizes) without unnecessarily increasing the complexity of the entire segment cell circuit.
3Productivity
If the digital input size is small, then the productivity of the communication system is maintained, but the manufacturing precision of the conversion process degrades
Solution Approach 1:
The DAC is pre-configured with multiple bit groups and corresponding segment cells, including the additional segment cell for the lowermost bit of the second bit group. This preliminary configuration ensures that when small digital input sizes occur during operation, the conversion precision is already optimized and ready to handle these cases without degrading manufacturing precision, while maintaining productivity.
Data Source
AI summary
A digital-to-analog converter (DAC) for generating an analog output from a digital input includes a controller configured to generate a control signal based on the digital input, and a segment cell circuit including a plurality of segment cells turned on or off based on the control signal and configured to generate the analog output based on outputs of the plurality of segment cells, wherein the plurality of segment cells include a plurality of first segment cells each configured to generate an output corresponding to each of bits included in a first bit group of the digital input, a plurality of second segment cells each configured to generate an output corresponding to each of bits included in a second bit group of the digital input, and an additional segment cell configured to generate an output corresponding to a lowermost bit among the bits included in the second bit group.