Segmented DAC Circuit for Small-Input Linearity and Dynamic Range
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Solution Overview
Problem
In communication systems like 5G that use Orthogonal Frequency Division Multiplexing (OFDM), digital-to-analog converters (DACs) face challenges in maintaining linearity and dynamic range performance, especially when dealing with small digital input sizes.
Innovation Solution
The implementation of a DAC that includes a controller generating a control signal based on the digital input, and a segment cell circuit with multiple segment cells turned on or off accordingly. This configuration includes additional segment cells to reduce errors during the conversion process, improving linearity and dynamic range performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the digital input into the DAC is small, then the DAC can handle small data sizes effectively, but linearity and dynamic range performance degrade due to errors in the conversion process
Solution Approach 1:
The digital input is divided into multiple bit groups (first bit group, second bit group, third bit group), and corresponding segment cells are used for each group. This segmentation allows the DAC to process small digital inputs more accurately by treating different bit groups separately, thereby improving linearity and dynamic range performance while maintaining the ability to handle small data sizes
Solution Approach 2:
The controller generates a control signal based on the digital input before the actual conversion process. This preliminary action allows the segment cells to be pre-configured according to the bit groups, enabling more accurate conversion from the outset and reducing errors that would otherwise degrade linearity and dynamic range performance
Data Source
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AI summary
A digital-to-analog converter (DAC) for generating an analog output from a digital input includes a controller configured to generate a control signal based on the digital input, and a segment cell circuit including a plurality of segment cells turned on or off based on the control signal and configured to generate the analog output based on outputs of the plurality of segment cells, wherein the plurality of segment cells include a plurality of first segment cells each configured to generate an output corresponding to each of bits included in a first bit group of the digital input, a plurality of second segment cells each configured to generate an output corresponding to each of bits included in a second bit group of the digital input, and an additional segment cell configured to generate an output corresponding to a lowermost bit among the bits included in the second bit group.