Segmented DAC Architecture for High Resolution and Low Loading Error
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Solution Overview
Problem
High-resolution digital-to-analog converters (DACs) face challenges due to high component count and area penalties, with sub-DACs causing linearity errors, glitches, and cross-talk due to capacitive loading, which complicates the reduction of component count and area.
Innovation Solution
The proposed solution involves an N-bit digital-to-analog converter and an M-bit sub-digital-to-analog converter architecture, where the N-bit converter handles most significant bits and the M-bit converter handles least significant bits, using a differential difference amplifier and current-mode digital-to-analog converters to minimize loading and reduce errors, and incorporating charge pumps for rail-to-rail operation and unity gain configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a sub-DAC is used to convert least significant bits, then component count and area are reduced, but capacitive loading causes linearity errors, glitches, and cross-talk
Solution Approach 1:
A buffer amplifier is introduced as an intermediary between the sub-DAC and the primary DAC output. This buffer isolates the capacitive loading effect, preventing it from affecting the primary DAC's linearity while allowing the sub-DAC to function with reduced component count and area.
Solution Approach 2:
The DAC is segmented into a primary DAC for most significant bits and a sub-DAC for least significant bits. The sub-DAC uses fewer components and occupies less area since it only needs to handle the least significant bits, while the buffer amplifier resolves the loading issue between segments.
2Device complexity
If sub-DAC component count is reduced, then overall DAC area is reduced, but loading effects increase causing errors and cross-talk
Solution Approach 1:
The buffer amplifier serves as a mediator that decouples the sub-DAC from the primary DAC output stage. This allows the sub-DAC to have reduced component count and lower capacitive loading, while the buffer prevents harmful loading effects from propagating back to affect linearity and cause cross-talk.
3Area of moving object
If the sub-DAC is made smaller to reduce area, then integration density increases, but output loading on the primary DAC increases
Solution Approach 1:
The buffer amplifier is positioned between the sub-DAC and primary DAC output to isolate the smaller sub-DAC from loading effects. This allows the sub-DAC to be compact with higher integration density while the buffer maintains output linearity by preventing excessive loading on the primary DAC.
Data Source
AI summary
A system includes an N-bit digital-to-analog converter and an M-bit sub-digital-to-analog converter. The N-bit digital-to-analog converter includes 2N resistances connected in series across first and second reference voltages and converts N most significant bits of B bits of data. The M-bit sub-digital-to-analog converter converts M least significant bits of the B bits of data. The M-bit sub-digital-to-analog converter includes a first converter that converts a voltage across one of the 2N resistances to a first current, a current-mode digital-to-analog converter that interpolates the first current and outputs a second current, and a second converter that converts the second current to an output voltage representing the N most significant bits and the M least significant bits of the B bits of data.