Segmented DAC Circuit for High Resolution in Minimal Area
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in reducing circuit area as the number of bits increases, leading to larger chip sizes and undesirable effects from parasitic capacitance in sample and hold circuits.
Innovation Solution
A DAC design that uses two decoders and control logic to process upper and lower data bits, along with a sample and hold circuit that minimizes parasitic capacitance effects by dividing the digital data into upper bits, a control bit, and a lower bit, and employs a selection circuit to manage reference voltages, reducing the overall circuit area and mitigating parasitic capacitance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits of the digital signal is increased to provide higher resolution output, then the output precision is improved, but the circuit area increases proportionally
Solution Approach 1:
The patent divides the digital signal processing into multiple segments by splitting the digital signal into upper bits and lower bits, which are processed by separate decoders. This segmentation allows the circuit to achieve high-resolution output without requiring a single large decoder, thus reducing the overall circuit area while maintaining output precision.
2Ease of manufacture
If conventional sample and hold circuit using operational amplifier is used, then the circuit implementation is simplified, but parasitic capacitance at input terminal causes undesirable effects on output
Solution Approach 1:
The patent extracts and removes the problematic operational amplifier from the sample and hold circuit configuration. By eliminating the OP-AMP, the source of parasitic capacitance at the input terminal is removed, thereby eliminating the undesirable effects on the DAC output while maintaining circuit functionality through an alternative implementation approach.
Data Source
AI summary
Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).