Segmented DAC Architecture for High-Speed, High-Resolution Output
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in high resolution and high frequency environments, with thermometer DACs requiring large chip space and binary DACs experiencing output signal integrity issues due to mismatched cell strengths and synchronization problems.
Innovation Solution
A digital-to-analog converter with a segmented architecture comprising least significant bit (LSB) and most significant bit (MSB) thermometer sub-converters, along with a binary converter, using cell pairs with main and dummy cells and dedicated voltage buffers to maintain cyclo-stationary voltage levels, reducing chip space and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a thermometer DAC is used for high resolution applications, then conversion precision is improved, but chip area increases significantly
Solution Approach 1:
The DAC is divided into multiple segments, each handling a specific range of digital input codes. Each segment contains a subset of the total cells required for a full-resolution thermometer DAC, thereby reducing the chip area while maintaining high conversion precision through segmented operation
Solution Approach 2:
Multiple thermometer DAC segments are nested within a single integrated structure, with each segment containing scaled-down versions of the cell architecture. This nesting approach allows high-resolution conversion precision to be achieved while compacting the overall chip area through hierarchical organization
2Area of stationary object
If a binary DAC is used to reduce chip space, then area is reduced, but output signal integrity deteriorates due to cell mismatch
Solution Approach 1:
Within each thermometer DAC segment, cells are designed with uniform local characteristics and matching topology to ensure consistent performance. The local quality of each cell is optimized to minimize mismatch effects, while the segmented architecture maintains overall area efficiency
Solution Approach 2:
The design transforms the binary-weighted cell structure into segmented thermometer structures where the number of cells and their weighting parameters are adjusted locally within each segment. This parameter transformation maintains signal integrity by ensuring proper current matching while reducing total chip area
3Speed
If binary DAC cells switch rapidly to reduce transition time, then speed is improved, but signal glitches increase due to synchronization issues
Solution Approach 1:
The segmented thermometer DAC structure enables periodic switching patterns within each segment, where cells switch in a controlled sequence rather than simultaneously. This periodic action within segments reduces the overall transition time while minimizing synchronization-related glitches through staged switching
Data Source
AI summary
A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (MSB) thermometer sub-converters. A binary converter can also be added. The LSB and MSB thermometer sub-converters include cell pairs with a main cell and a dummy cell. The main cell switches according to actual data, drawing power from a voltage source at each transition. To maintain a consistent voltage level at the output, the dummy cell creates a transition to draw power from the voltage source responsive to a lack of transition in the main cell. Each cell pair has a dedicated voltage source. Also, the MSB thermometer sub-converter can include a load matching circuit to match the parasitic capacitance of the LSB thermometer sub-converter at an output.