Segmented DAC Linearization With Redundancy Mapping
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) face challenges in achieving linearization due to nonlinearity issues, such as differential and integral non-linearity, which affect their spectral performance and signal-to-noise ratio, and are exacerbated by component mismatches and thermal noise.
Innovation Solution
The implementation of redundancy mapping and probabilistic assignment techniques in DACs, where the input digital word is decomposed into segments, and redundant representations are generated and mapped with specific probabilities to produce an output analog signal, effectively reducing nonlinearity by distributing mismatches as random noise across the Nyquist band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DAC architectures are used, then hardware complexity is reduced, but nonlinearity (DNL and INL) increases due to component mismatches
Solution Approach 1:
The input digital word is divided into multiple segments, each processed by separate sub-DACs. This segmentation allows independent processing of different bit groups, enabling redundancy mapping to be applied to each segment while distributing the overall conversion across multiple simpler hardware blocks rather than requiring a single complex high-resolution DAC
Solution Approach 2:
A digital signal processing block serves as an intermediary between the input digital word and the sub-DACs. This intermediary performs redundancy mapping and probabilistic assignment, transforming the input into multiple redundant representations that are then distributed to sub-DACs. This mediator handles the complexity of linearization in the digital domain rather than requiring complex analog circuitry
2Manufacturing precision
If high-resolution DACs are used, then linearity improves, but power consumption increases
Solution Approach 1:
The conversion process is segmented across multiple lower-resolution sub-DACs rather than using a single high-resolution DAC. Each sub-DAC operates at reduced resolution, consuming less power individually. The cumulative power consumption of multiple low-resolution sub-DACs is less than that of a single high-resolution DAC achieving the same effective linearity through redundancy mapping
Solution Approach 2:
Multiple redundant representations of the input digital word are created and mapped to different sub-DACs. Instead of using one high-precision converter, the system creates multiple copies of the conversion function at lower precision levels. These redundant conversion paths are combined to achieve the desired linearity performance while keeping individual power consumption low
3Manufacturing precision
If component matching is improved, then nonlinearity reduces, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The system accepts component mismatches as inevitable but converts this previously harmful factor into a beneficial one through probabilistic assignment. Instead of trying to eliminate mismatches through precise manufacturing, the invention randomly assigns components to different positions across multiple conversions. This randomization causes mismatch errors to manifest as uncorrelated noise rather than systematic nonlinearity, effectively converting manufacturing imperfections into acceptable performance
Solution Approach 2:
A digital processing intermediary performs redundancy mapping that decouples performance from manufacturing precision. This digital mediator handles the complexity of compensation, allowing standard off-the-shelf components with typical tolerances to be used. The digital processing layer compensates for analog imperfections without requiring precision-matched components
4Manufacturing precision
If redundancy mapping with probabilistic assignment is implemented, then linearity improves and becomes independent of component mismatches, but processing complexity increases
Solution Approach 1:
The processing complexity is segmented and distributed across multiple independent sub-DACs and processing blocks rather than concentrated in a single complex unit. Each segment handles a portion of the redundancy mapping independently, allowing parallel processing and reducing the complexity burden on any single processing element
Solution Approach 2:
The system uses itself to handle the processing complexity through feedback loops and iterative refinement. The digital signal processing block continuously monitors and adjusts the redundancy mapping based on observed performance, allowing the system to self-optimize rather than requiring external complex control mechanisms
Data Source
AI summary
Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.