Segmented DAC Linearization With Redundant Mapping
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges in achieving perfect linearity due to mismatches in unit elements, leading to differential non-linearity (DNL) and integral non-linearity (INL) errors, which affect the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR), making it difficult to process analog signals accurately.
Innovation Solution
The implementation of a two-segment DAC architecture with redundant mapping and probabilistic assignment, where the input is decomposed into two segments with a redundant representation, allowing for perfectly linear output by averaging the outputs of sub-DACs, thereby eliminating DNL errors and maintaining linearity despite component mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DAC architecture with unit elements is used, then device complexity is reduced, but manufacturing precision deteriorates due to mismatches causing DNL and INL errors
Solution Approach 1:
The input digital signal is segmented into two parts: a first segment with most significant bits and a second segment with least significant bits. Each segment is processed by a separate sub-DAC with different resolution requirements. This segmentation allows the system to achieve high overall precision without requiring all unit elements to have identical precision, thereby resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
Different segments of the input signal are processed with different levels of precision according to their significance. The first segment (MSBs) is processed by a sub-DAC with coarser resolution, while the second segment (LSBs) is processed by a sub-DAC with finer resolution. This local quality approach ensures that precision is applied where needed, improving overall DAC linearity without uniformly increasing device complexity across all components.
2Measurement precision
If higher resolution DAC is implemented, then signal-to-noise ratio is improved, but device complexity increases due to more unit elements requiring precise matching
Solution Approach 1:
The high-resolution DAC is segmented into multiple sub-DACs handling different bit ranges. The first sub-DAC processes MSBs with coarser resolution, while the second sub-DAC processes LSBs with finer resolution. This segmentation achieves the required signal-to-noise ratio for high-resolution conversion without requiring a single monolithic DAC with all unit elements precisely matched, thereby reducing overall device complexity.
3Manufacturing precision
If ideal component matching is required, then manufacturing precision is improved, but ease of manufacture deteriorates due to difficulty in achieving precise matches
Solution Approach 1:
The patent applies different precision requirements to different segments of the DAC. The first sub-DAC handling MSBs requires less precise component matching, while the second sub-DAC handling LSBs requires more precise matching. This local quality approach improves overall manufacturing precision where critical (in the LSB path) while maintaining ease of manufacture in less critical areas (MSB path), resolving the contradiction between manufacturing precision and ease of manufacture.
Data Source
AI summary
The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.