Segmented DAC Architecture With Low Switch Count and Stable Impedance
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Solution Overview
Problem
Conventional string DACs require a large number of resistors and switches, leading to increased integrated circuit area and high output impedance that varies with the DAC input code, resulting in inconsistent settling times for switched capacitor circuits.
Innovation Solution
A digital to analog converter architecture that combines coarse and fine resolution resistor circuits with reduced numbers of switches and resistors, using a modified R-2R network to achieve a differential output with constant impedance and consistent settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional N-bit string DAC uses 2^N resistors and 2^N switches, then the DAC achieves the required resolution, but the integrated circuit area increases rapidly and the output impedance becomes large and varies widely with input code
Solution Approach 1:
The patent divides the conventional single resistor string into multiple parallel resistor strings. Each string contains fewer resistors and switches, reducing the area required per string. By paralleling multiple strings, the circuit achieves the same resolution while reducing total area and lowering output impedance through parallel combination effects.
2Measurement precision
If a conventional N-bit string DAC uses 2^N switches, then the DAC achieves the required resolution, but the number of switches and decode circuitry increases, reducing circuit speed due to parasitic capacitances
Solution Approach 1:
The patent segments the switch matrix into multiple smaller groups corresponding to parallel resistor strings. Each group handles fewer switches, reducing the total switch count and associated parasitic capacitances. This segmentation maintains resolution while improving speed by reducing the capacitive loading that limits switching performance.
3Measurement precision
If a conventional string DAC uses a large number of series-connected resistors, then the DAC achieves the required resolution, but the output impedance becomes large and varies over a wide range with respect to the DAC input code
Solution Approach 1:
The patent divides the resistor string into multiple parallel segments, each with fewer series resistors. This segmentation reduces the output impedance of each segment and, when combined in parallel, achieves a lower overall output impedance that varies less with input code, improving ease of operation and stability.
Solution Approach 2:
The patent combines multiple parallel resistor strings to achieve the desired resolution while maintaining low and stable output impedance. The parallel combination of multiple strings with fewer series resistors each results in an equivalent circuit that has both the required resolution and improved output impedance characteristics.
Data Source
AI summary
A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1−Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.