Segmented DAC Switch Configuration for Lower Chip Area
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) require a large number of switches, leading to increased chip area and power consumption as the bit number of the digital value increases, making them inefficient for applications like liquid crystal display (LCD) source drivers.
Innovation Solution
A DAC configuration using a gamma voltage generator and a decoder with a first and second selector, where the decoder employs a first thermometer encoder to generate a 2N-bit code from N bits of the digital value, reducing the number of switches required by approximately 33% through a selecting-group configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional binary selector configuration is used, then digital-to-analog conversion function is achieved, but the number of switches increases significantly with bit number, leading to increased chip area and power consumption
Solution Approach 1:
The M-bit digital value is divided into two parts: N bits processed by the first thermometer encoder and (M-N) bits processed by the second thermometer encoder. This segmentation allows the switching network to be divided into multiple stages, reducing the number of switches required in each stage while maintaining the overall conversion accuracy.
Solution Approach 2:
The patent introduces a two-stage decoding architecture that transforms the conventional single-stage binary selector into a multi-dimensional structure. The first selector processes N bits and the second selector processes (M-N) bits, creating a hierarchical switching network that reduces the switch count from exponential to linear growth with respect to bit number.
2Area of stationary object
If the number of switches is reduced to decrease chip area, then manufacturing efficiency improves, but circuit functionality may be compromised
Solution Approach 1:
The chip area is efficiently utilized by segmenting the switching network into two stages. The first selector handles N bits and the second selector handles (M-N) bits, allowing compact arrangement of switches while maintaining full M-bit processing capability. This segmentation enables the circuit to process high-bit digital values without requiring proportionally large chip area.
Solution Approach 2:
The dual-encoder architecture provides multi-functionality: the first thermometer encoder processes N bits and the second processes (M-N) bits, together enabling complete M-bit digital value conversion. This universal design allows the same circuit structure to handle various bit depths by adjusting the division between N and (M-N).
3Measurement precision
If more switches are used to improve conversion precision, then digital-to-analog accuracy increases, but power consumption increases
Solution Approach 1:
The power consumption is reduced by segmenting the switching network into two stages. Instead of using a single large switching network that would consume significant power, the first selector with 2^N switches and the second selector with 2^(M-N) switches divide the power load, maintaining voltage selection accuracy while reducing total power consumption.
4Reliability
If conventional binary selector architecture is used, then complete digital value conversion is achieved, but gamma coupling increases
Solution Approach 1:
The gamma coupling is reduced by segmenting the selector into two stages. The first selector processes N bits and the second selector processes (M-N) bits, which distributes the signal paths and reduces the coupling effect between gamma voltages. This segmentation maintains complete conversion capability while minimizing the harmful gamma coupling effect.
Data Source
AI summary
A DAC includes a gamma voltage generator for generating a plurality of gamma voltages, and a decoder for receiving an M-bit digital value for selecting one of the gamma voltages, wherein the decoder comprises a first thermometer encoder, a first selector and a second selector. The first thermometer encoder is utilized to receive N bits of the digital value to generate a first thermometer code with 2N bits, wherein N is smaller than M, and M and N are positive integers. The first selector has a plurality of selecting groups, each selecting group having 2N switches controlled by the first thermometer code to output one gamma voltage, where the second selector receives the gamma voltages outputted by the selecting groups of the first selector and outputs one gamma voltage selected from the received gamma voltages based on the (M−N) bit of the digital value.