Segmented DAC Cross-Coupled Capacitors for Slice Timing Alignment
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Solution Overview
Problem
Existing high-speed, high-resolution digital-to-analog converters (DACs) with lower segmentation ratios face timing misalignment between unary, intermediate significant bit (ISB), and least significant bit (LSB) slices due to imperfect impedance scaling, leading to higher order harmonics and degraded noise spectral density (NSD) and spurious-free dynamic range (SFDR).
Innovation Solution
Incorporating cross-coupled capacitive elements in the unary slices of a segmented DAC, which adds an additional delay to the output current, aligning the timing of the output currents from unary, ISB, and LSB slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If lower segmentation ratio is used in high-speed DAC, then device complexity is reduced, but timing misalignment between unary, ISB, and LSB slices occurs due to imperfect impedance scaling
Solution Approach 1:
The patent introduces cross-coupled capacitive elements that modify the timing parameters of the unary slices by adding controlled delay. This changes the electrical characteristics (capacitance values, coupling strengths) to compensate for timing misalignment caused by lower segmentation ratios, thereby resolving the contradiction between reduced device complexity and maintained timing precision.
2Manufacturing precision
If cross-coupled capacitive elements are added to unary slices, then timing alignment of output currents is improved, but device complexity increases
Solution Approach 1:
The capacitive elements are segmented and distributed specifically within the unary slices rather than being applied uniformly across all slices. This targeted segmentation allows timing correction to be applied only where needed (in the unary cell), minimizing the overall increase in device complexity while achieving the desired timing alignment improvement.
3Measurement precision
If timing alignment is achieved through cross-coupled capacitive elements, then noise spectral density and spurious-free dynamic range are improved, but additional circuit elements increase manufacturing complexity
Solution Approach 1:
The cross-coupled capacitive elements serve multiple functions simultaneously: they provide timing alignment correction, maintain impedance matching, and contribute to overall signal integrity. This multi-functionality means that a single structural addition addresses multiple performance requirements, reducing the need for separate corrective circuits and thereby easing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The alignment of output currents improves the noise spectral density (NSD) and spurious-free dynamic range (SFDR) of the DAC, reducing higher order harmonics and enhancing the overall performance of the converter.
Implementation Method 1
each of the unary slices comprising a set of cross-coupled capacitive elements. The set of cross-coupled capacitive elements includes first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors
Data Source
AI summary
A digital-to analog converter (DAC) includes an unary cell comprising unary slices, the unary slices are coupled in parallel, an intermediate significant bit (ISB) cell comprising ISB slices, the ISB slices are coupled in parallel, and a least significant bit (LSB) cell comprising LSB slices, the LSB slices are coupled in parallel, the unary cell, the ISB cell and the LSB cell each being coupled to each other, each of the unary slices comprising a set of cross-coupled capacitive elements including first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors, and second capacitive elements having a first end coupled to a node positioned between a third pair of transistors and a second end coupled to a node positioned between a fourth pair of transistors.