Segmented DAC Architecture for High-Resolution Voltage Settling
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Solution Overview
Problem
High-resolution digital-to-analog converters (DACs) face challenges in achieving high speed and settling accuracy due to self-heating and load changes, particularly in applications requiring precision output voltage settling beyond 10 bits, and current steering array structures necessitate high output currents that degrade settling accuracy.
Innovation Solution
A fast segmented DAC architecture with a string DAC stage followed by an interpolation amplifier stage, utilizing delta-sigma modulation and a 2M-string resistor configuration with CMOS transmission gate switches and differential transistor pairs, achieves high resolution and fast settling by reducing resistor string impedance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current source array structures are used to achieve high resolution (16-bits), then fine resolution is improved, but self-heating occurs due to large currents (20 mA) forced through resistors, causing precision voltage settling errors
Solution Approach 1:
The DAC is divided into two stages: a string DAC stage for MSB conversion and an interpolation amplifier sub-DAC stage for LSB conversion. This segmentation allows the string DAC to operate at lower currents while the interpolation amplifier provides the fine resolution, avoiding self-heating in the resistor string while maintaining 24-bit resolution capability.
Solution Approach 2:
The interpolation amplifier acts as an intermediary between the string DAC output and the final high-resolution output. It takes the coarse voltage from the string DAC and interpolates it to achieve fine resolution without requiring large currents through the resistor string, thereby eliminating self-heating problems.
2Stability of the object's composition
If voltage division (string DAC) is used to achieve monotonicity and output voltage stability, then these characteristics are improved, but conversion speed is limited due to inherent RC time constants
Solution Approach 1:
The conversion process is segmented into two phases: fast coarse conversion by the string DAC that establishes monotonicity and stability, followed by faster fine conversion by the interpolation amplifier that operates with smaller voltage swings and lower time constants, achieving both stability and high speed.
Solution Approach 2:
The problem is solved by adding a temporal dimension to the conversion process, using sequential two-stage conversion rather than simultaneous single-stage conversion. This allows different parts of the conversion to occur at different time scales, optimizing both speed and stability.
3Measurement precision
If the number of resistors in the resistor string is increased to achieve higher resolution (e.g., 10 or 12 bits), then resolution is improved, but the voltage difference between string DAC tap voltages is reduced to 1-4 millivolts, causing DNL problems due to random variation in transconductance of differential input transistor pairs
Solution Approach 1:
The resolution is segmented between the string DAC (providing MSB with larger voltage steps) and the interpolation amplifier (providing LSB with finer resolution). This allows the string DAC to use fewer resistors with larger voltage differences, avoiding transconductance variation problems, while the interpolation amplifier achieves the additional resolution through a different mechanism.
Solution Approach 2:
The interpolation amplifier serves as an intermediary that converts the limited-resolution output of the string DAC into high-resolution output. It uses a different conversion mechanism that is not limited by the small voltage differences in the resistor string, thereby achieving high resolution without the DNL problems that would result from increasing the number of string resistors.
Data Source
AI summary
A string DAC having 2M string resistors includes a plurality of switches for selectively coupling, according to the decoding of an M-bit MSB subword, the voltage across a string resistor to an interpolation sub-DAC which interpolates it according to the decoding of an N-bit mid-subword. The voltage across the string resistor is multiplexed, according to the decoding of an N-bit mid-subword, to various inputs of 2N differential transistor pairs of an interpolation amplifier. A P-bit delta sigma modulator produces a delta sigma modulated signal, according to a P-bit LSB subword, to control multiplexing of voltages on the terminals of the string resistor to an input of one of the differential transistor pairs selected by decoding of the N-bit mid-subword to monotonically average a contribution of the selected differential transistor pair to generation of an output voltage representing a word including the M-bit, N-bit, and P-bit subwords.