Segmented Data Buffer for DRAM Latency Reduction
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Solution Overview
Problem
DRAM is not well suited for managing rapid and continuous influxes of small data samples due to inefficiencies such as frequent row activations, increased refresh cycles, higher power consumption, and greater memory access latency.
Innovation Solution
A data buffer, such as SRAM, is used to temporarily store small data samples in a segmented memory mode or qualified store memory mode, allowing for efficient handling of rapid data generation and reducing the frequency of DRAM accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used for storing small data samples, then storage capacity is achieved, but power consumption increases and access latency increases
Solution Approach 1:
The memory system is segmented into two distinct parts: SRAM for storing small data samples and DRAM for bulk storage. This segmentation allows each memory type to operate in its optimal performance regime, with SRAM handling frequent small writes without incurring DRAM's high power consumption and latency penalties
Solution Approach 2:
SRAM acts as an intermediary buffer between the data source and DRAM storage. Small data samples are first written to SRAM, which then batches and transfers data to DRAM in larger, more efficient operations, reducing the frequency of DRAM row activations and refresh cycles
2Quantity of substance
If DRAM is used for storing small data samples, then storage capacity is achieved, but memory access latency increases
Solution Approach 1:
The memory system is segmented into two distinct parts: SRAM for storing small data samples and DRAM for bulk storage. This segmentation allows each memory type to operate in its optimal performance regime, with SRAM handling frequent small writes without incurring DRAM's high power consumption and latency penalties
Solution Approach 2:
SRAM acts as an intermediary buffer between the data source and DRAM storage. Small data samples are first written to SRAM, which then batches and transfers data to DRAM in larger, more efficient operations, reducing the frequency of DRAM row activations and refresh cycles
3Productivity
If circular buffer mode is used in SRAM, then write efficiency is improved, but data loss may occur when buffer is full
Solution Approach 1:
The system merges circular buffer mode (for continuous overwriting when full) with selective data transfer to DRAM. The circular buffer ensures write efficiency by allowing continuous operation, while periodic transfers to DRAM prevent permanent data loss by archiving important samples before they are overwritten
Solution Approach 2:
The system dynamically changes operational parameters based on buffer status. When SRAM is full, it continues writing in circular mode but increases the frequency of transfers to DRAM, effectively changing the data retention strategy based on buffer occupancy to prevent data loss
Data Source
AI summary
One example method occurs at a device having a data buffer operating in a segmented memory mode or a qualified store memory mode. The method includes: during an initial phase and prior to an end condition being met, iteratively providing a write pointer indicating one of a first set of memory locations of a first memory segment of the data buffer, wherein iteratively providing the write pointer includes updating the write pointer to a next memory location of the first set of memory locations in a circular manner after acquisition data from a data source is stored in a current memory location; and in response to the end condition being met, changing the write pointer to indicate one of a second set of memory locations of a second memory segment of the data buffer.