Segmented Data Line Layout for Low-Voltage-Drop Array Substrates
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Solution Overview
Problem
As display panels increase in size and resolution, the length and number of gate lines and data lines also increase, leading to significant voltage drops due to inherent resistance, which affects the performance and reliability of display devices.
Innovation Solution
The array substrate design includes a base with gate lines and data lines disposed on it, with an insulating layer between the line segments. The data lines are composed of alternating first and second line segments, with the second line segments positioned near the gate lines and the first line segments away from them. This configuration ensures electrical connection through vias in the insulating layer, reducing voltage drops and preventing data gate shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the length and number of gate lines and data lines are increased to achieve larger display panels with higher resolution, then the display size and resolution are improved, but the voltage drop increases due to inherent resistance
Solution Approach 1:
The data lines are divided into multiple segments (first data line segments and second data line segments) that are spatially separated and connected through pixel circuits. This segmentation allows the data transmission path to be broken into shorter sections, reducing the cumulative voltage drop across the entire data line while maintaining high resolution display capabilities
Solution Approach 2:
Pixel circuits serve as intermediary components that connect segmented data line portions. These intermediary pixel circuits provide local signal regeneration and distribution, enabling the data lines to be divided into shorter segments without compromising the overall data transmission integrity across the high-resolution display panel
2Device complexity
If data lines are routed close to gate lines to reduce complexity, then device complexity is reduced, but data gate shorts may occur
Solution Approach 1:
Data lines are segmented into first and second data line segments that are positioned on opposite sides of gate lines. This segmentation creates natural spatial separation between data and gate lines, preventing direct contact and potential shorts while maintaining a compact overall layout that does not significantly increase device complexity
Solution Approach 2:
The layout transitions from a planar two-dimensional arrangement to a three-dimensional stacked configuration where first data line segments and second data line segments are positioned at different vertical levels relative to gate lines. This dimensional change enables close proximity routing while maintaining electrical isolation through the vertical separation provided by the insulating layer
3Reliability
If data lines are divided into multiple segments positioned at different sides of gate lines, then voltage drops are reduced and data gate shorts are prevented, but the manufacturing process complexity increases
Solution Approach 1:
The data transmission lines are divided into first data line segments and second data line segments that are formed in different manufacturing steps. This segmentation enables independent formation and optimization of each segment, allowing standard manufacturing processes to be applied to each portion separately, thereby managing overall manufacturing complexity while achieving the reliability benefits of segmented routing
Solution Approach 2:
The insulating layer with via holes is formed in advance before the data line segments are deposited. This preliminary preparation of the insulating structure with pre-defined via hole positions enables subsequent data line segments to be accurately positioned and connected without requiring complex real-time alignment procedures, thus reducing manufacturing process complexity
Data Source
AI summary
An array substrate includes gate lines, data lines and an insulating layer. The data lines all extend in a first direction, and the gate lines all extend in a second direction, the first direction intersecting the second direction. A data line includes first line segments and second line segments that all extend in the first direction and are arranged alternately. The second line segments are disposed at a side of the gate lines proximate to the base, and the first line segments are disposed at a side of the gate lines away from the base. There is no overlap among orthographic projections of the first line segments on the base and orthographic projections of the gate lines on the base. The insulating layer includes first vias. In the first direction, any two adjacent first line segments are electrically connected to a second fine segment through at least two first vias.