Segmented DEM DAC Architecture for ISI-Suppressed Linearity
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Solution Overview
Problem
Digital-to-analog converters (DACs) face distortion due to non-ideal circuit behavior, particularly element mismatches and nonlinear inter-symbol interference (ISI), which affect the accuracy of multi-bit DAC outputs.
Innovation Solution
A high linearity digital-to-analog conversion circuit employing segmentation and dynamic element matching techniques, using a combination of rotated pulse width modulation (PWM) and data weighted averaging (DWA) algorithms to reduce ISI errors, with noise-shaped segmentation and adaptive start pointer adjustments in the rotated PWM technique.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional multi-bit DAC designs are used, then the circuit implementation is straightforward, but element mismatches and nonlinear ISI cause significant distortion in the output
Solution Approach 1:
The multi-bit digital input is segmented into multiple 1-bit streams using noise-shaped segmentation, which distributes the conversion task across multiple 1-bit DACs. This segmentation approach improves output linearity by enabling the use of simpler 1-bit DAC elements while reducing the impact of element mismatches through the segmentation and recombination process.
Solution Approach 2:
The patent applies dynamic element matching (DEM) techniques that dynamically adjust the mapping between digital input bits and physical DAC elements based on measured element characteristics. By changing the assignment parameters of DAC elements in real-time, the system compensates for element mismatches and reduces distortion without requiring higher precision hardware.
2Manufacturing precision
If 1-bit DACs are used with instantaneous switching, then the circuit design is simple, but practical non-ideal behavior introduces signal-dependent transient errors and ISI
Solution Approach 1:
The system performs preliminary characterization of each 1-bit DAC element's transient response and switching behavior during calibration. This preliminary action stores correction data that is applied during normal operation to compensate for signal-dependent transient errors and ISI, improving accuracy without adding complex real-time control mechanisms.
Solution Approach 2:
The patent implements feedback-based DEM techniques where the actual output of each 1-bit DAC is monitored and used to dynamically adjust the input sequencing and element selection. This feedback loop compensates for transient errors and ISI by adapting the digital-to-analog mapping based on observed performance, improving transient accuracy through closed-loop control.
3Manufacturing precision
If dynamic element matching techniques are applied, then ISI errors are reduced, but the hardware complexity and power consumption increase
Solution Approach 1:
The patent applies DEM techniques selectively to the most significant bits or critical portions of the digital input where ISI has the greatest impact. By applying DEM only where necessary rather than to all bits uniformly, the system achieves adequate ISI reduction while minimizing the additional hardware complexity and power consumption associated with full DEM implementation.
Data Source
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AI summary
A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.