Segmented Digital VFC Circuit for Memory Failbit Counting
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Solution Overview
Problem
Existing VFC circuits in memory devices occupy space and increase power consumption, and their accuracy is affected by factors like power drop, transistor mismatch, and signal routing, leading to undercounting and yield loss.
Innovation Solution
A digital VFC circuit with a counter that counts fail bits in binary format, comprising multiple counter stages and reception stages with switches, allowing for high-accuracy counting of verification results without reliance on current sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an analog method is used to sense failbit numbers, then the VFC circuit can be implemented with simpler circuitry, but current sensing is required which is impacted by power drop, transistor mismatch, and signal routing leading to undercounting
Solution Approach 1:
The patent replaces the analog current-based sensing method with a digital voltage-based counting method. Instead of using current sensing that is susceptible to power drop and transistor mismatch, the invention uses digital logic circuits that operate on voltage levels, thereby eliminating the measurement precision issues associated with analog current sensing while maintaining circuit functionality.
Solution Approach 2:
The patent changes the fundamental parameter used for failbit detection from current (analog) to voltage (digital). This parameter change transforms the sensing mechanism into a digital domain where voltage levels represent logical states, making the system immune to the analog imperfections of power drop and transistor mismatch that plague current-based sensing.
2Measurement precision
If a digital VFC circuit is implemented to improve counting accuracy, then failbit counting is unaffected by power fluctuations and transistor mismatches, but the circuit occupies more space and increases power consumption
Solution Approach 1:
The patent divides the digital VFC circuit into multiple parallel counting paths or stages, each handling a portion of the verification bits. This segmentation allows the circuit to process multiple bits simultaneously through parallel operations, reducing the overall circuit area compared to a sequential approach while maintaining digital accuracy. The segmented structure also enables modular design that optimizes space utilization.
3Measurement precision
If a digital VFC circuit is implemented to improve counting accuracy, then failbit counting is unaffected by power fluctuations and transistor mismatches, but power consumption increases
Solution Approach 1:
The patent implements the digital VFC circuit to operate in periodic batches rather than continuously. The circuit processes verification bits in discrete groups during specific time windows, allowing other circuitry to remain idle or in low-power states during non-counting periods. This periodic operation reduces average power consumption compared to continuous operation while maintaining the accuracy benefits of digital counting when active.
Data Source
AI summary
A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.