Segmented Drain Doping for Semiconductor ESD Protection
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Solution Overview
Problem
Integrated chips (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses, which can cause voltage spikes that exceed threshold voltages, leading to damage such as 'blowing out' of gate dielectrics or 'melting' of active regions. Existing solutions have not provided sufficient ESD protection to meet the specifications for certain applications, like HBM ESD class 2 and greater devices.
Innovation Solution
The IC incorporates a semiconductor device with a drain region comprising two or more first doped regions and one or more second doped regions. The first doped regions have a higher concentration of dopants than the second doped regions, and the second doped regions are disposed laterally between the first doped regions, resulting in a high resistance across the drain region. This design helps mitigate the impact of ESD pulses by reducing the voltage spike across the drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ESD protection designs are used, then basic ESD protection is provided, but the voltage spike across the drain region during ESD events exceeds threshold voltages, causing damage to gate dielectrics or active regions
Solution Approach 1:
The drain region is segmented into multiple first doped regions and second doped regions arranged in series, creating a distributed resistance structure that limits voltage spikes during ESD events while maintaining normal device operation
Solution Approach 2:
Different doped regions are assigned different doping concentrations - first doped regions have higher concentration for lower on-resistance during normal operation, while second doped regions have lower concentration to contribute to voltage limiting during ESD events, creating localized functional differences within the drain region
2Reliability
If the drain region is designed with high resistance to reduce voltage spikes, then ESD protection is improved, but the device may have increased on-resistance affecting normal operation
Solution Approach 1:
The drain region structure provides dynamic resistance characteristics - during normal operation the high doping concentration regions dominate providing low on-resistance, while during ESD events the overall structure presents high resistance to limit voltage spikes, achieving context-dependent performance
Solution Approach 2:
The patent optimizes doping concentrations, region dimensions, and arrangements to achieve the desired balance between on-resistance and ESD protection, using parameter adjustments to tune the trade-off between normal operation performance and ESD event protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced ESD protection design effectively reduces the voltage at critical regions of the semiconductor device, preventing damage from ESD pulses. This solution enables the IC to meet or exceed specifications for applications requiring high ESD protection, such as HBM ESD class 2 and greater devices.
Implementation Method 1
The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.