Segmented High-Speed Driver Circuit for Slew Rate Control
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Solution Overview
Problem
The existing high-speed signal driving circuits in USB2.0 standards face challenges in maintaining precise control over signal rising and falling times due to limitations in adjusting voltage amplitude and slew rate, especially with larger capacitance loads, which affects signal transmission quality.
Innovation Solution
A driving circuit with a delay adjuster and multiple drivers that generate signals with varying delay times, along with an assist driver to add a fixed current, allowing for precise control of signal flipping speed and reducing rising and falling times by adjusting the delay time of the delayers and output currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed rated current is used in the back-stage driver, then the output voltage amplitude can be maintained at a fixed level, but the signal rising and falling times cannot be precisely controlled
Solution Approach 1:
The driver circuit is segmented into multiple parallel drivers (first driver, second driver, third driver, fourth driver) instead of using a single back-stage driver. Each driver can be independently controlled with different delay times, allowing precise adjustment of signal rising and falling times by selectively enabling combinations of drivers based on load conditions.
Solution Approach 2:
The circuit transitions from a static fixed current approach to a dynamic adaptive current approach. The control circuit dynamically selects and adjusts the number of active drivers and their respective delay times based on real-time load conditions, enabling precise control of signal transitions while adapting to varying capacitance loads.
2Speed
If the load capacitance increases, then the signal transmission distance or capability is improved, but the signal rising and falling times increase
Solution Approach 1:
The control circuit performs preliminary assessment of the load capacitance and pre-configures the appropriate combination of drivers and their delay times before signal transmission. This allows the system to be optimized for the specific load condition in advance, ensuring fast signal transitions even when driving larger capacitance loads.
Solution Approach 2:
The system changes multiple parameters simultaneously - the number of active drivers, the delay time of each driver, and their parallel configuration - to adapt to varying load capacitance. By adjusting these parameters based on load conditions, the system maintains fast signal transmission speed while accommodating different capacitance values.
3Manufacturing precision
If multiple drivers with different delay times are used, then the signal rising and falling times can be precisely controlled, but the device complexity increases
Solution Approach 1:
Multiple drivers are designed with identical circuit structures and functionalities, each capable of operating independently with a specific delay time. This universal design allows the system to achieve precise timing control through parallel configuration rather than requiring complex individual driver designs, simplifying the overall control logic.
Solution Approach 2:
A control circuit acts as an intermediary that manages the complexity of coordinating multiple drivers. The control circuit receives timing requirements, selects appropriate driver combinations, and configures their delay times, thereby isolating the complexity from the main signal transmission path and enabling precise timing control through centralized management.
4Reliability
If the signal flipping speed is increased, then the transmission quality is improved, but the control precision over rising and falling times deteriorates
Solution Approach 1:
The system uses periodic adjustment of driver delay times and configurations to optimize signal transitions. By periodically assessing transmission conditions and adjusting driver parameters, the system maintains both high flipping speed and precise timing control, adapting to changing load conditions while ensuring reliable signal transmission.
Data Source
AI summary
A high-speed signal driving device includes an assist driver, a delay adjuster, and a plurality of drivers. The assist driver receives a control signal and is coupled to a first output node and a second output node to output a first current to the first output node or the second output node. The delay adjuster receives the control signal to generate a plurality of delay signals. Each of the delay signals has a different delay time corresponding to the control signal. One of the drivers receives the control signal, and other drivers correspondingly receive the plurality of delay signals. The plurality of drivers are coupled to the first output node and the second output node via a first output end and a second output end.