Segmented Digital-to-Time Converter for Low-Jitter Fractional-N PLLs
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Solution Overview
Problem
Fractional-N phase lock loops (PLLs) face challenges in generating high precision frequency outputs with low clock jitter due to instantaneous frequency errors and high deterministic jitter, which can be mitigated but result in increased oscillator noise and non-linear digital-to-time converter (DTC) performance.
Innovation Solution
A multi-stage digital-to-time converter with local synchronization logic circuits is introduced, which dynamically adjusts the output clock phase and minimizes jitter by using a set of buffers to reduce transistor noise and duty cycle degradation, achieving low Integral Non-Linearity (INL) and RMS jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional-N PLL is used to generate high precision frequency outputs, then frequency precision is improved, but deterministic jitter increases
Solution Approach 1:
The DTC is divided into multiple delay stages (first delay stage, second delay stage, etc.), each with its own local synchronization logic circuit. This segmentation allows independent optimization of each stage's timing characteristics, reducing overall deterministic jitter while maintaining frequency precision.
Solution Approach 2:
Local synchronization logic circuits are used to pre-synchronize the digital-to-time converter code and reset pulse with the local input clock and output clock of each delay stage before processing. This preliminary synchronization action eliminates timing uncertainties and reduces deterministic jitter in the final output.
2Measurement precision
If mitigation techniques are applied to reduce instantaneous frequency errors, then frequency precision is improved, but oscillator noise increases
Solution Approach 1:
Multiple delay stages with local synchronization logic circuits act as intermediary elements between the input clock and output clock. These intermediaries process and condition the signals, reducing the need for aggressive mitigation techniques that would otherwise increase oscillator noise.
3Reliability
If a multi-stage DTC with local synchronization is used, then deterministic jitter is reduced, but device complexity increases
Solution Approach 1:
The DTC is divided into multiple delay stages (first delay stage, second delay stage, etc.), each with its own local synchronization logic circuit. This segmentation allows independent optimization of each stage's timing characteristics, reducing overall deterministic jitter while maintaining frequency precision.
Solution Approach 2:
Each delay stage is designed with identical functionality (delay element plus local synchronization logic), allowing the same circuit block to be replicated multiple times. This modular universal design reduces overall complexity compared to a monolithic DTC with centralized synchronization logic.
4Productivity
If high reference frequencies are used, then productivity is improved, but timing margins become more stringent
Solution Approach 1:
Local synchronization logic circuits are used to pre-synchronize the digital-to-time converter code and reset pulse with the local input clock and output clock of each delay stage before processing. This preliminary synchronization action eliminates timing uncertainties and reduces deterministic jitter in the final output.
Solution Approach 2:
The DTC dynamically adjusts delay characteristics through local synchronization logic that adapts to the specific timing requirements of each delay stage. This dynamic adjustment capability allows the system to maintain adequate timing margins even at high reference frequencies where static timing analysis would fail.
Data Source
AI summary
A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.