Semiconductor Wiring Layout With Segmented Dummy Sidewalls
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Solution Overview
Problem
Existing side wall processing in semiconductor manufacturing faces challenges such as pattern shape constraints, microloading effects, dishing effects, and short circuits due to variations in pattern density and spatial frequency, leading to reduced yield and complexity in manufacturing small-scale semiconductor devices.
Innovation Solution
The method involves forming sacrificial layers with specific patterns in functioning and dummy areas, using these layers as masks to etch concavities, and filling conductive or insulating materials, while ensuring the sacrificial layers in dummy areas are separated into multiple components to minimize spatial frequency changes and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If side wall processing is used to form detailed patterns exceeding lithography resolution limits, then pattern resolution is improved, but unnecessary wiring patterns are generated causing short circuits
Solution Approach 1:
The sacrificial layer pattern is divided into multiple separate components (first through fourth sacrificial layers) rather than forming a continuous pattern. This segmentation prevents the formation of unnecessary wiring patterns that could cause short circuits, while still enabling the side wall processing to achieve the desired pattern resolution for functional wirings.
Solution Approach 2:
Different regions of the substrate are treated differently: functional areas receive sacrificial layers for pattern formation, while dummy areas receive separated sacrificial layer components that prevent short circuits. This local differentiation allows the same side wall processing technique to achieve both high resolution and reliability in different locations.
2Manufacturing precision
If pattern density varies significantly depending on positions, then etching speed changes causing microloading effect, but uniform pattern density is difficult to achieve
Solution Approach 1:
The pattern density parameter is actively controlled by adjusting the configuration and distribution of sacrificial layers in dummy areas. By changing the density parameter in non-functional regions, the overall pattern density becomes more uniform across the substrate, which equalizes etching speed and prevents microloading effects.
3Area of stationary object
If continuous sacrificial layer pattern is formed in dummy areas, then pattern coverage is improved, but dishing effect occurs during CMP process
Solution Approach 1:
The sacrificial layer pattern in dummy areas is segmented into multiple separated components rather than forming a continuous layer. This segmentation reduces the overall pattern coverage in dummy regions, which prevents the dishing effect that occurs during CMP processing, while still maintaining adequate coverage in functional areas.
4Length of moving object
If side wall processing is used to reduce wiring width and spacing, then device scale is reduced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is simplified by segmenting the sacrificial layer formation into discrete, separable components with regular patterns. This segmentation makes the additional processing steps more manageable and less complex than forming continuous intricate patterns, thereby reducing the overall manufacturing complexity while still achieving reduced wiring dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of microloading and dishing effects, enhances yield, and simplifies the manufacturing process by minimizing short circuits, allowing for the production of smaller, more reliable semiconductor devices.
Implementation Method 1
forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask
Data Source
AI summary
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.