Segmented ECC Circuit for Faster Memory Error Correction

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Solution Overview

Problem

As semiconductor memory devices, particularly DRAMs, experience increased data errors due to reduced cell sizes, existing error correction codes face challenges in balancing improved error correction capability with a simplified structure.

Innovation Solution

An error correction code (ECC) circuit is implemented with a syndrome calculating unit, error location detecting unit, and error correcting unit, utilizing a H-matrix and Galois field to generate syndromes and error vectors, allowing for efficient error correction with a simplified structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction capability is improved to handle increased data errors in smaller memory cells, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidECC circuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The ECC circuit is segmented into three functional units: syndrome calculating unit, error location detecting unit, and error correcting unit. Each unit performs a specific function in the error correction process, allowing for modular design and simplified implementation while maintaining strong error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs Galois field arithmetic and H-matrix based syndrome calculation to change the mathematical parameters of the error correction process. This approach enables efficient error detection and correction with reduced computational complexity compared to traditional methods.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If traditional error correction methods are used to ensure accurate error correction, then reliability is improved, but processing time increases

Engineering Contradiction:

Improveerror correction accuracyVSAvoiderror vector generation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The syndrome calculating unit pre-calculates syndromes based on the received data and H-matrix before error location detection. This preliminary action enables the error location detecting unit to quickly determine error positions without performing complex calculations, thereby reducing processing time while maintaining correction accuracy.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces traditional mechanical or brute-force error detection methods with Galois field arithmetic and polynomial-based error location detection. This substitution significantly reduces computation time while maintaining or improving error correction accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12354689B2Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code

Publication Date: 2025.07.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.