Segmented ECC Circuit for High-Bit Memory Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems, particularly those utilizing quantum mechanical effects like MRAM, face challenges in correcting a large number of error bits due to the exponential increase in circuit complexity required for error correction, which affects operation speed and the number of correctable bits.
Innovation Solution
An ECC circuit is implemented with a first and second sub-ECC circuit, an output multiplexer, and a control logic circuit to manage the distribution of error bits, allowing efficient correction of errors by utilizing two sub-ECC circuits to handle different numbers of error bits, thereby reducing circuit complexity and improving operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of error bits that the ECC circuit may correct is increased, then the error correction capability is improved, but the circuit configuration complexity increases exponentially
Solution Approach 1:
The patent divides the ECC circuit into multiple sub-ECC circuits, each responsible for correcting a specific subset of error bits. This segmentation allows the system to handle a larger total number of error bits without requiring a single exponentially complex circuit, thereby resolving the contradiction between error correction capability and circuit complexity.
2Reliability
If the circuit configuration for error correction is increased to correct more error bits, then the number of correctable bits is improved, but the operation speed deteriorates
Solution Approach 1:
By segmenting the ECC circuit into parallel sub-ECC circuits that can operate simultaneously on different error bit subsets, the patent achieves both increased error correction capability and maintained operation speed. The parallel architecture eliminates the speed penalty that would otherwise result from a single large-scale ECC circuit.
3Device complexity
If a single ECC circuit is used to correct all error bits, then the circuit configuration is simple, but the number of error bits that can be corrected is limited
Solution Approach 1:
The patent segments the error correction function across multiple sub-ECC circuits, each handling a portion of the total error bits. This approach maintains relative circuit simplicity while enabling the system to correct a larger total number of error bits than a single circuit could handle alone.
Solution Approach 2:
The patent implements a universal error correction mechanism where multiple sub-ECC circuits can be configured to handle different numbers and types of error bits. This multi-functionality allows the system to adapt to various error conditions while maintaining a relatively simple overall circuit configuration.
Data Source
AI summary
Disclosed is an ECC circuit, which includes a first sub-ECC circuit to correct a first error including first error bits; a second sub-ECC circuit to correct a second error including second error bits; an output multiplexer circuit to output a plurality of bits, wherein a first plurality of bits among the plurality of bits is output to the first sub-ECC circuit, and wherein a second plurality of bits among the plurality of bits is output to the second sub-ECC circuit; and a control logic circuit configured to control the output multiplexer circuit, and wherein the control logic circuit is further configured to: control the output multiplexer circuit to output at least one of the first error bits to the second sub-ECC circuit based on a number of the first error bits exceeding a first number and a number of the second error bits is less than the first number.