Segmented Uppermost Electrode for 3D Memory Reliability
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in increasing integration density and reliability due to limitations in patterning technology, which affects their cost and performance.
Innovation Solution
The solution involves a three-dimensional semiconductor memory device structure with an electrode structure comprising alternately stacked electrodes and insulating patterns on a substrate, where the uppermost electrode is divided into physically isolated segments, and vertical active patterns penetrating the electrode structure, with an electrode-dielectric layer between each vertical active pattern and electrode, and additional features like capping dielectric patterns for physical isolation and interconnections for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are fabricated using existing patterning technology, then integration density can be increased, but reliability is degraded
Solution Approach 1:
The uppermost electrode is divided into multiple physically isolated segments arranged in the first direction. This segmentation reduces stress concentration and prevents catastrophic failure across the entire electrode, thereby improving reliability while maintaining the three-dimensional structure for high integration density
Solution Approach 2:
Capping dielectric patterns are introduced as intermediary elements between the segmented uppermost electrode and the underlying structure. These capping dielectric patterns provide mechanical support and stress relief, acting as a buffer that enhances device reliability without compromising the vertical stacking architecture
2Productivity
If process technology is improved to form finer patterns, then integration density increases, but fabrication cost increases due to expensive equipment and process complexity
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical stacking, where multiple electrodes and insulating patterns are stacked alternately in the vertical direction. This dimensional change allows integration density to increase without requiring finer lateral patterning, thereby avoiding the need for expensive advanced lithography equipment
Solution Approach 2:
By segmenting the uppermost electrode into multiple sections, the patent enables the use of existing patterning technology to create the segmented structure through simpler processes, avoiding the need for costly cutting-edge lithography while still achieving high integration through vertical stacking
Data Source
AI summary
Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.