Semiconductor Layout With Segmented Epitaxy for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and effective suppression of short channel effects while maintaining improved yield and performance.
Innovation Solution
The semiconductor device incorporates a substrate with specific active patterns and gate structures, including epitaxial patterns of varying conductivity types, arranged in a manner that allows for multi-bridge channels, enhancing current control and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors with 3D channels are used to increase integration density and suppress short channel effects, then current control capability is enhanced, but device complexity increases
Solution Approach 1:
The device is divided into multiple active patterns (first, second, third, fourth) arranged in a specific configuration with different pitch ratios. Each active pattern has epitaxial patterns on specific sides, creating segmented functional regions that collectively achieve superior current control while managing complexity through modular arrangement
Solution Approach 2:
The invention transitions from conventional planar transistor structures to a multi-dimensional configuration where active patterns are arranged both laterally (with different pitches in different regions) and vertically (epitaxial patterns on sides of gate). This dimensional expansion enables enhanced current control capability without linearly increasing gate length
2Productivity
If epitaxial patterns are disposed between all active patterns to improve yield, then manufacturing yield improves, but device complexity increases
Solution Approach 1:
Epitaxial patterns are selectively disposed only on specific sides of specific gate patterns rather than uniformly between all active patterns. The first gate pattern has epitaxial patterns on its first and second sides, while the second gate pattern has epitaxial patterns on its third and fourth sides, creating local variations that optimize yield without excessive complexity
Solution Approach 2:
Instead of placing epitaxial patterns between all possible active patterns, the invention applies epitaxial patterns partially - specifically on the sides of gate patterns that benefit most from this configuration. This partial application achieves improved yield while avoiding the complexity of complete coverage
Data Source
AI summary
There is provided a semiconductor device with improved yield and performance. The semiconductor device includes a substrate including a first region and a second region and having a first conductivity type, first and second active patterns spaced apart by a first pitch, on the first region, a first gate structure intersecting the first and second active patterns, first epitaxial patterns each having a second conductivity type, different from the first conductivity type, and receiving the same voltage level, on both sides of the first gate structure on each of the first and second active patterns, third and fourth active patterns spaced apart by a second pitch, on the second region, a second gate structure intersecting the third and fourth active patterns, and second epitaxial patterns each having the second conductivity type, on the sides of the second gate structure on each of the third and fourth active patterns, wherein the first pitch is n times the second pitch (where n is a natural number of 2 or greater), and no epitaxial pattern having the second conductivity type is disposed between the first and second active patterns