Segmented FeRAM Plate Lines for Layout Flexibility

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Solution Overview

Problem

Ferroelectric random access memory (FeRAM) arrays face issues with endurance reduction and increased power consumption due to unnecessary data-restoring writes and size constraints from the layout of sense amplifiers and read/write circuits within the paired bit line pitch.

Innovation Solution

The FeRAM array is segmented into sections with electrically unconnected plate lines, allowing only one section to be selected for read operations, reducing unnecessary writes and enabling the distribution of sense amplifiers and read/write circuits beyond the bit line pair pitch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the FeRAM array uses a single plate line shared by all FeRAM cells, then the layout of sense amplifiers and read/write circuits is constrained within the paired bit line pitch, but this causes increased power consumption and reduced endurance due to unnecessary data-restoring writes

Engineering Contradiction:
Improvelayout flexibility of sense amplifiers and read/write circuitsVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent divides the FeRAM array into multiple sections, each with its own dedicated plate line. This segmentation allows independent selection of specific sections for read operations, preventing unnecessary writes to other sections and reducing overall power consumption while providing layout flexibility for sense amplifiers and read/write circuits.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the FeRAM array uses a single plate line shared by all FeRAM cells, then the circuit layout is simplified, but this causes reduced endurance and increased power consumption due to unnecessary data-restoring writes

Engineering Contradiction:
Improvecircuit layout complexityVSAvoidendurance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the FeRAM array into multiple sections with electrically isolated plate lines. This allows the circuit layout to be organized in a systematic way while enabling selective access to specific sections. The segmentation prevents unnecessary write operations to unselected sections, thereby improving endurance without excessively increasing overall circuit complexity.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If the FeRAM array allows simultaneous selection of multiple sections, then access flexibility is improved, but this requires more complex plate line control and increases power consumption

Engineering Contradiction:
Improvesection selection flexibilityVSAvoidplate line control complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates multiple independent sections with electrically isolated plate lines, each可控 by its own plate line selection cell. This segmentation provides flexibility to select any section independently while keeping the control mechanism relatively simple, as each section has its own dedicated control path without interfering with other sections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces plate line selection cells as intermediary components between the plate line selection signal and the actual plate lines. These selection cells act as switches that connect or disconnect specific plate lines based on selection signals, providing flexible section selection while managing control complexity through a standardized intermediary interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9972374B1Ferroelectric random access memory (FeRAM) array with segmented plate lines that are electrically-isolated from each other
Publication Date: 2018.05.15 PASCALINE SYSTEMS INC
  • US9972374B1 patent drawing
  • US9972374B1 patent drawing
  • US9972374B1 patent drawing

AI summary

A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the first plate line and the second plate line are electrically unconnected, and wherein only the first section of FeRAM cells or the second section of FeRAM cells, but not both, are selected for a read operation at any given time. In each section of the FeRAM cells, a plate line selection cell connects the corresponding plate line to a plate line selection line. Each FeRAM cell in each section is read or written over a pair of bit lines running in a direction transverse to the word line of the section, and the plate line selection line runs along a direction parallel to the bit lines.