Segmented Ferroelectric Memory Plate Reduces Parasitic Capacitance
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Solution Overview
Problem
Non-volatile memory devices, such as ferroelectric RAM, face significant power consumption issues due to parasitic capacitances when a single plate is activated for accessing memory cells, leading to increased energy usage and potential data loss in volatile memory devices like DRAM.
Innovation Solution
Implementing a memory array with segmented plates, where each plate portion is energized independently, reducing parasitic capacitance and power consumption by isolating unaccessed plate portions and using plate drivers to activate only the necessary plate portions for read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single plate is activated for accessing memory cells, then memory access operation is enabled, but parasitic capacitance increases leading to high power consumption
Solution Approach 1:
The memory plate is divided into multiple segmented portions, allowing selective activation of only the necessary plate segments during memory access operations. This segmentation reduces the overall parasitic capacitance that needs to be charged and discharged, thereby lowering power consumption while maintaining full memory access functionality.
2Ease of operation
If a single plate is activated for accessing memory cells, then memory access operation is enabled, but parasitic capacitance increases leading to data loss in volatile memory
Solution Approach 1:
By segmenting the memory plate into multiple portions, the parasitic capacitance is distributed and reduced, preventing charge leakage that would cause data loss. This ensures data integrity is maintained during memory access operations in volatile memory devices.
3Use of energy by moving object
If the size of components is limited to reduce power consumption, then power consumption decreases, but memory access capability is reduced
Solution Approach 1:
The plate segmentation enables selective activation of only the necessary plate portions during memory access operations. This maintains full memory access capability across the entire memory array while reducing power consumption by keeping unaccessed plate portions in a low-power state.
Solution Approach 2:
The system dynamically activates only the required plate segments based on the memory access pattern, allowing the memory access capability to remain fully functional while adapting power consumption to the actual operational needs.
Data Source
AI summary
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.