Segmented Fin Cladding for Ge III-V Epitaxial Growth
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Solution Overview
Problem
Conventional semiconductor processes face challenges in scaling down multi-gate transistors, particularly due to constraints on fin length and compliance, leading to suboptimal epitaxial growth and increased defects in Ge and III-V channel devices.
Innovation Solution
Decoupling the active channel fin length from the typical fin length of 2× gate pitch and recessing the central segment to enable improved compliant growth, using cladding layers on shorter fin portions to enhance compliance and free surface relaxation, allowing for higher quality epitaxial growth in Ge and III-V channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin length is reduced to enable scaling and increased device density, then device density and capacity increase, but epitaxial growth quality deteriorates and defects increase
Solution Approach 1:
The fin structure is segmented into discrete portions along its length, with cladding layers applied selectively to specific segments rather than the entire fin. This segmentation allows the active channel region to have optimized compliance for epitaxial growth while maintaining the overall fin length required for device density
Solution Approach 2:
Different regions of the fin are given different properties through selective cladding layer placement. The active channel portion receives cladding layers that provide compliance and promote defect-free epitaxial growth, while other portions may have different treatments or no cladding, optimizing each region for its specific function
2Ease of manufacture
If the fin length is constrained to 2× gate pitch in conventional processes, then fabrication simplicity is maintained, but compliance and free surface relaxation are insufficient leading to increased defects
Solution Approach 1:
The fin is divided into multiple segments along its length, with cladding layers applied to specific segments. This allows the active channel region to be optimized for compliance and defect-free growth, while maintaining compatibility with conventional fabrication processes that use standard gate pitch dimensions
Solution Approach 2:
The cladding layer acts as an intermediary between the fin structure and the epitaxial growth process. It provides the necessary compliance and free surface relaxation to enable high-quality epitaxial growth without requiring changes to the underlying fin geometry or conventional fabrication workflows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved compliance and reduced defects, enabling better performance and integration of high mobility materials in semiconductor devices, particularly at smaller technology nodes like 14 nanometers and beyond.
Implementation Method 1
cladding layers on shorter fin portions to enhance compliance and free surface relaxation
Implementation Method 2
enabling better performance and integration of high mobility materials in semiconductor devices
Data Source
AI summary
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.