Segmented FinFET Gate Structure for Contact and Channel Control

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling down semiconductor devices like MOSFETs and finFETs, leading to increased complexity and difficulty in minimizing short channel effects and enlarging contact openings while maintaining performance and cost-effectiveness.

Innovation Solution

The implementation of finFET structures with varying gate lengths, where gate portions above the fin surfaces have a shorter length to enlarge contact openings and those below have a longer length to minimize short channel effects, along with the use of epitaxial source/drain regions and specific dielectric and conductive materials to enhance performance and manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the gate length is reduced to enlarge contact openings, then the contact opening size is improved, but short channel effects worsen

Engineering Contradiction:
Improvecontact opening sizeVSAvoidshort channel effects
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The gate structure is segmented into two distinct portions: a first gate portion with a first length and a second gate portion with a second length. This segmentation allows each portion to serve different functional requirements - the first gate portion optimizes contact opening size while the second gate portion minimizes short channel effects, thereby resolving the technical contradiction between contact opening enlargement and short channel effect suppression.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate structure are assigned different local properties through varying gate lengths. The first gate portion has a specific length optimized for contact opening formation, while the second gate portion has a different length optimized for channel control. This local differentiation enables simultaneous optimization of both contact opening size and short channel effect mitigation in different spatial locations.

Inventive Principle:
Principle #3Local quality

2Reliability

If the gate length is increased to minimize short channel effects, then the short channel effects are improved, but contact opening size worsens

Engineering Contradiction:
Improveshort channel effectsVSAvoidcontact opening size
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The gate structure is divided into two portions with different lengths, allowing the second gate portion to provide sufficient length for minimizing short channel effects while the first gate portion maintains adequate contact opening size. This segmentation resolves the contradiction by distributing different functional requirements to different segments rather than requiring a uniform gate length.

Inventive Principle:
Principle #1Segmentation

3Productivity

If the device dimensions are scaled down to increase storage capacity and processing speed, then the storage capacity and processing speed are improved, but manufacturing complexity worsens

Engineering Contradiction:
Improveprocessing speedVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The gate structure employs local quality differentiation with varying gate lengths in different portions, enabling optimized performance at scaled dimensions without proportionally increasing manufacturing complexity. This localized optimization allows the device to achieve high processing speed and storage capacity while maintaining relatively manageable manufacturing complexity through a structured, non-uniform design.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10741672B2Gate structure for semiconductor device
Publication Date: 2020.08.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10741672B2 patent drawing
  • US10741672B2 patent drawing
  • US10741672B2 patent drawing

AI summary

A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.