Segmented FinFET Gate Layout for Stable Insulation Distance
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Solution Overview
Problem
There is a challenge in developing integrated circuit devices that can maintain a stable insulation distance between wirings and contacts within a small device area, while also optimizing performance as integrated circuit devices continue to downscale.
Innovation Solution
The integrated circuit device includes a substrate with fin-type active areas, gate lines, cut gate lines, and power wiring, which are strategically arranged to reduce device area and enhance performance. This configuration involves a substrate with multiple active areas, gate lines crossing these areas, and cut gate lines with separation insulation layers to optimize spacing and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated circuit devices are downscaled to reduce device area, then device area is reduced, but insulation distance between wirings and contacts becomes unstable
Solution Approach 1:
The gate line is divided into multiple segments (first gate line, cut gate line, second gate line) with gate cut areas between them. This segmentation allows for the insertion of separation insulation layers that provide stable insulation distance while maintaining compact device area through the fin-type active area configuration.
Solution Approach 2:
Separation insulation layers are introduced as intermediary elements between adjacent gate lines and between gate lines and power wiring. These intermediary layers ensure stable insulation distance is maintained even as device dimensions are reduced through downscaling.
2Area of stationary object
If device area is reduced through downscaling, then device area is reduced, but performance optimization becomes difficult
Solution Approach 1:
The active area is transformed into a fin-type structure that extends vertically from the substrate. This dimensional change allows increased effective area for transistor operation without proportionally increasing the planar device footprint, thereby maintaining performance while reducing device area.
Solution Approach 2:
Different regions of the device are assigned different functions: fin-type active areas for high-performance transistor operation, gate cut areas with separation insulation for electrical isolation and parasitic capacitance reduction, and power wiring regions for electrical supply. This local differentiation optimizes overall device performance within reduced area.
3Area of stationary object
If gate lines are placed close together to reduce area, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
Separation insulation layers are positioned between adjacent gate lines and between gate lines and power wiring to act as electrical intermediaries. These layers reduce parasitic capacitance by providing insulation while allowing the gate lines to remain in close proximity for area efficiency.
Solution Approach 2:
Gate lines are extracted from continuous structures and divided into separate segments (first gate line, cut gate line, second gate line) with gaps between them. This extraction allows separation insulation layers to be inserted, reducing parasitic capacitance while maintaining compact layout.
Data Source
AI summary
An integrated circuit device includes substrate including a fin-type active area extending on the substrate in a first direction parallel to an upper surface of the substrate, a first gate line crossing the fin-type active area on the substrate and extending in a second direction perpendicular to the first direction, a cut gate line extending in the second direction and being spaced apart from the first gate line with a first gate cut area therebetween, a second gate line extending in the second direction and being spaced apart from the cut gate line with a second gate cut area therebetween, and a power wiring disposed on the cut gate line.