Segmented Flash Writes for Read-Write Collision Reduction
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Solution Overview
Problem
Higher bit density in flash memory leads to increased read-write collisions, resulting in unpredictable read latency and reduced performance in solid state storage devices.
Innovation Solution
Implementing a segmented write process that groups program loops into distinct write segments separated by a dwell time, allowing for staggered writing and reading operations to improve data retention, error rates, and threshold voltage margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher bit density flash memory cells are used, then storage capacity increases, but read-write collisions increase causing unpredictable read latency
Solution Approach 1:
The patent segments the flash memory array into multiple independent channels, each capable of handling read and write operations simultaneously. This spatial segmentation allows parallel access patterns where reads and writes occur in different physical locations, reducing collisions while maintaining high storage capacity through multi-level cell technology
2Reliability
If more program loops are used to write data, then data retention and error rates improve, but write time increases
Solution Approach 1:
The patent implements periodic verify operations within the program loop structure, where verification is performed at regular intervals rather than continuously. This periodic action maintains data retention and error rate performance by ensuring proper programming while reducing the total number of operations needed, thereby decreasing write time
Solution Approach 2:
The patent employs feedback mechanisms where verify results from previous program loops inform subsequent programming operations. This allows the system to adapt the number and intensity of program loops based on actual cell state, achieving reliable data retention with optimized write time by avoiding unnecessary additional programming cycles
3Reliability
If segmented writes with dwell time are implemented, then read-write collisions decrease, but write operation duration increases
Solution Approach 1:
The patent maintains continuity of useful action by overlapping read operations on one channel with write operations on another channel during the dwell time periods. This parallel execution ensures that the system remains productive throughout the entire write operation duration, minimizing the net impact on overall system performance while still achieving collision reduction
Data Source
AI summary
Systems and methods are disclosed for writing data to a non-volatile memory (NVM) using a segmented write process. The NVM uses a plurality of program loops to write data to the NVM. The NVM groups the plurality of program loops into a plurality of write segments, and each write segment includes a distinct set of the plurality of program loops. The write segments are separated by a dwell time that allows read access before the data is written to the NVM.