Capacitorless Memory Cell With Segmented Floating Body
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Solution Overview
Problem
Current memory devices face challenges in improving the operating margin and data retention characteristics due to voltage fluctuations and discharging of signal charges in memory cells, particularly in dynamic random access memory (DRAM) and twin-transistor MOS transistor memory elements.
Innovation Solution
A dynamic flash memory cell structure is developed with a semiconductor base surrounded by gate insulating and conductor layers, where voltages applied to the source line, bit line, selection gate line, and plate line are controlled to perform page erasing and writing operations, allowing for the retention and reading of at least three-valued logic storage data, and optionally four-valued data by gradually increasing voltages during writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor without capacitor is used for memory cell, then device complexity is reduced, but operating margin and data retention characteristics deteriorate due to voltage fluctuation and charge discharging
Solution Approach 1:
The memory cell is segmented into two separate MOS transistors (first and second transistors) with isolated floating body channels, allowing independent charge storage and read operations. This segmentation resolves the technical contradiction by enabling reliable data retention while maintaining the capacitorless structure.
Solution Approach 2:
The invention transitions from a single-transistor planar structure to a two-transistor three-dimensional configuration with vertically stacked or laterally arranged floating body channels. This dimensional change allows simultaneous charge storage and selective reading, improving reliability while keeping the device relatively simple.
2Loss of information
If hole group is stored in the channel for data retention, then data storage capability is achieved, but operating margin reduces due to voltage fluctuation from capacitive coupling
Solution Approach 1:
The floating body channel is divided into two isolated segments (first and second floating body channels) that can independently store charge. This segmentation allows one channel to store data while the other performs read operations, eliminating the voltage fluctuation problem that reduces operating margin.
Solution Approach 2:
The gate electrodes act as intermediaries to selectively control and read the charge stored in each floating body channel without directly disturbing the stored data. This intermediary mechanism enables reliable reading while maintaining data integrity and operating margin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating margin and data retention characteristics by effectively managing the hole group within the semiconductor base, enabling the storage and retrieval of multiple-valued logic data with improved efficiency and capacity.
Implementation Method 1
Within the semiconductor base, a hole group formed by an impact ionization phenomenon is retained
Data Source
AI summary
In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity layer and a second impurity layer at both ends in an extension direction of the semiconductor base, and at least two (first and second) gate conductor layers. The first impurity layer is connected to a source line, the second impurity layer to a bit line, one of the first or second gate conductor layer to a selection gate line, and the other to a plate line. Voltages applied to the source line, bit line, selection gate line, and plate line are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have logic storage data that is at least three-valued.