Segmented Floating Gate Memory Device Fabrication
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Solution Overview
Problem
Conventional non-volatile memory cells with floating gates face challenges in high aspect ratios of gaps between neighboring floating gates, leading to small control gate fill-in windows and lithographic overlap windows, which affect the coupling ratio and data storage efficiency.
Innovation Solution
The memory device features a data storage structure with a lower part and an upper part, where the upper part is narrower than the lower part, and a process involving recessing and dividing the data storage layer with spacers and a patterned hard mask layer to form floating gates, reducing the aspect ratio of gaps and increasing the control gate fill-in window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gap between two neighboring floating gates is reduced to increase surface area and gate coupling ratio, then the surface area for each floating gate is increased, but the aspect ratio of the gap becomes high making the control gate fill-in window small
Solution Approach 1:
The floating gate structure is segmented into two distinct parts: a lower part with larger width and an upper part with smaller width. This segmentation allows the lower part to provide sufficient surface area for coupling while the upper part creates a larger, more accessible gap for control gate formation, thereby resolving the contradiction between maximizing surface area and maintaining manufacturable gap dimensions.
Solution Approach 2:
The invention transitions from a conventional uniform-width floating gate to a multi-dimensional structure with varying width along its height. By introducing dimensional variation (wider at bottom, narrower at top), the design simultaneously achieves large effective area for coupling and adequate gap width for fabrication, overcoming the two-dimensional limitation of traditional rectangular floating gates.
2Reliability
If the gap between two neighboring floating gates is reduced to increase gate coupling ratio, then the gate coupling ratio is increased, but the lithographic overlap window in forming the floating gates becomes small
Solution Approach 1:
By dividing the floating gate into lower and upper portions with different widths, the invention creates a structure where the lower wide portion ensures strong coupling ratio while the upper narrow portion provides adequate spacing for lithographic processes. This segmentation resolves the conflict between achieving high coupling ratio and maintaining sufficient lithographic overlap window.
Solution Approach 2:
Different portions of the floating gate are given different local properties: the lower part has larger width optimized for coupling, while the upper part has smaller width optimized for lithographic formation. This local differentiation allows each region to fulfill its specific function without compromising the other, resolving the contradiction between coupling ratio and lithographic feasibility.
3Area of stationary object
If the process linewidth is small to increase integration density, then the surface area for each floating gate is increased, but the aspect ratio of the gap becomes high affecting control gate formation
Solution Approach 1:
The invention resolves the aspect ratio problem by introducing vertical dimensionality variation. Instead of maintaining a uniform width that would create high aspect ratios in narrow gaps, the floating gate width varies vertically (wider at bottom, narrower at top), effectively reducing the critical gap dimensions while preserving the total coupling area through the extended lower portion.
Solution Approach 2:
The segmented structure separates the functions of area generation and gap management into different vertical zones. The lower segment provides the necessary surface area for coupling, while the upper segment manages the gap dimensions to maintain acceptable aspect ratios, thereby resolving the contradiction between area requirements and aspect ratio constraints.
Data Source
AI summary
A memory device is described, including a substrate, data storage structures over the substrate, control gates over the data storage structures, and a dielectric layer between the data storage structures and the control gates, wherein each data storage structure includes a lower part and an upper part narrower than the lower part. A process for fabricating the memory device is also described, wherein formation of the data storage structures includes recessing portions of a data storage layer to form respective upper parts of the data storage structures and then dividing the recessed portions of the data storage layer to form respective lower parts of the data storage structures.