Segmented FTL Table Structure for Flash Memory Address Mapping
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Solution Overview
Problem
Flash memory devices have a large flash translation layer (FTL) that consumes significant space, necessitating a method to efficiently manage logical and physical addresses while reducing the size of the FTL table.
Innovation Solution
The method involves dividing the nonvolatile memory device into clusters, sub-clusters, and subsub-clusters, where logical pages are stored in a selected sub-cluster according to a given order of logical addresses, and generating tables to map these addresses to physical pages, thereby reducing the size of the FTL table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional FTL table is used to map logical addresses to physical addresses, then address mapping functionality is provided, but the FTL table consumes a large amount of flash memory space
Solution Approach 1:
The FTL table is segmented into multiple levels: a first FTL table storing mappings for first logical pages, and a second FTL table storing mappings for second logical pages. This segmentation allows the total FTL table size to be distributed and managed in smaller units, reducing the space consumption of any single FTL table while maintaining comprehensive address mapping coverage.
Solution Approach 2:
The patent introduces a hierarchical dimension to the FTL table structure by organizing logical pages into different levels (first logical pages and second logical pages) with corresponding FTL tables. This multi-level organization transforms a single large flat table into a structured hierarchy, enabling more efficient space utilization while preserving address mapping functionality.
2Device complexity
If logical pages are stored sequentially according to logical address order, then address mapping becomes simpler, but memory space utilization decreases
Solution Approach 1:
Logical pages are segmented into first logical pages and second logical pages, with each segment mapped by a corresponding FTL table. This segmentation enables the system to maintain simplified mapping within each segment while improving overall space utilization through selective placement strategies across different segments.
Solution Approach 2:
Different FTL tables are assigned to different logical page segments with potentially different mapping strategies. The first FTL table handles first logical pages while the second FTL table handles second logical pages, allowing each segment to be optimized locally for both mapping simplicity and space efficiency according to its specific characteristics.
Data Source
AI summary
A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.