Segmented GaN on SiC Wafer Stress Management
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Solution Overview
Problem
The growth of cubic gallium nitride (GaN) on silicon carbide (SiC) wafers faces challenges with material stress and wafer bow, which are not adequately addressed by existing technologies.
Innovation Solution
A semiconductor structure is created with monocrystalline silicon carbide layers on a silicon wafer, interspersed with amorphous and/or polycrystalline silicon carbide layers, and monocrystalline and amorphous/polycrystalline gallium nitride layers, where the gallium nitride layers are grown in segments to neutralize stress across the wafer, reducing bow and mechanical deficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If GaN is grown on a SiC wafer, then the heterogrowth process enables LED and power device applications, but material stress and wafer bow problems occur
Solution Approach 1:
The patent applies segmentation by dividing the continuous SiC layer into spaced-apart monocrystalline SiC layers with amorphous/polycrystalline SiC layers in between. This segmentation creates discrete stress zones that prevent stress accumulation across the entire wafer, thereby reducing wafer bow while maintaining the heterogrowth capability for LED and power device applications
Solution Approach 2:
The patent implements local quality by creating regions with different SiC crystal structures (monocrystalline vs amorphous/polycrystalline) at different locations on the wafer. The monocrystalline regions provide high-quality GaN growth sites, while the amorphous/polycrystalline regions act as stress relief zones, allowing each local area to serve its specific function
2Adaptability or versatility
If GaN is grown on a SiC wafer, then LED and power device applications are enabled, but wafer bow increases
Solution Approach 1:
By segmenting the SiC layer structure into spaced-apart monocrystalline layers, the patent limits the span over which stress can cause bowing. The amorphous/polycrystalline SiC layers between the monocrystalline layers act as stress breakers, maintaining wafer flatness while preserving the overall structure for device fabrication
Solution Approach 2:
The amorphous and/or polycrystalline SiC layers serve as intermediary regions between the monocrystalline SiC layers. These intermediary layers mediate the stress distribution, absorbing and redistributing stress to prevent excessive wafer bow while still allowing the heterogrowth process to proceed for LED and power device applications
3Stress or pressure
If tensile stress is distributed across the entire wafer, then stress relief is achieved, but wafer bow and cracking risk increase
Solution Approach 1:
The patent segments the stress distribution by creating spaced-apart monocrystalline SiC layers rather than a continuous layer. This segmentation confines tensile stress to localized regions between the monocrystalline layers, preventing stress from accumulating across the entire wafer and thereby reducing the risk of wafer bow and cracking
Solution Approach 2:
The patent creates local quality differences by having monocrystalline SiC layers at specific positions and amorphous/polycrystalline SiC layers in between. This arrangement ensures that stress is managed locally in the amorphous/polycrystalline regions, while the monocrystalline regions maintain structural integrity, collectively preserving wafer reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer bow and stress by segmenting the gallium nitride growth, ensuring that tensile stress is limited to die dimensions rather than the entire wafer, preventing cracking and maintaining wafer flatness.
Implementation Method 1
The second gallium nitride layers may be configured to reduce wafer stress and bow-causing forces
Data Source
AI summary
We disclose a semiconductor structure comprising a monocrystalline silicon wafer; spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.