Segmented FinFET Gate Stack With Air Gaps for Lower Capacitance
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Solution Overview
Problem
Current semiconductor IC chip technologies face challenges in improving electrical characteristics, particularly in reducing device capacitance to minimize resistive-capacitive delay, despite advancements in scaling down semiconductor manufacturing.
Innovation Solution
The process involves forming a semiconductor structure with gate stacks, isolation regions, and non-conformally depositing a refill dielectric layer in cut metal gate trenches to create air gaps, which reduces the overall dielectric constant and capacitance by partitioning the gate stacks into sections, thereby decreasing the distance between metal fill layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor IC chip is scaled down with increased functional density, then the number of electrical devices per chip area increases, but the device capacitance increases leading to increased resistive-capacitive delay
Solution Approach 1:
The gate stack is divided into multiple sections by introducing cut metal gate trenches that partition the gate stack along the channel length direction. This segmentation creates multiple shorter gate sections instead of one long gate, reducing the overall capacitance while maintaining the same functional density and chip area utilization.
Solution Approach 2:
Air gaps (porous structure) are introduced between the gate stack sections by filling the cut metal gate trenches with dielectric material that creates void spaces. This porous structure reduces the dielectric constant in the gate region, thereby lowering the gate capacitance and reducing resistive-capacitive delay without affecting the functional density.
2Loss of time
If the gate stack is partitioned into sections to reduce capacitance, then the resistive-capacitive delay decreases, but the device complexity increases
Solution Approach 1:
The gate stack segmentation is achieved through a systematic process of forming cut metal gate trenches at specific positions, which divides the gate stack into multiple manageable sections. This segmentation reduces capacitance and delay while the structured approach keeps the complexity可控 through standardized trench formation and filling processes.
Solution Approach 2:
Dielectric material is introduced as an intermediary substance to fill the cut metal gate trenches and create air gaps between gate sections. This intermediary material facilitates the capacitance reduction by providing electrical isolation and creating porous structures, while the process itself can be integrated into existing manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the overall capacitance of the semiconductor device by 1% to 2%, enhancing electrical characteristics and reducing resistive-capacitive delay.
Implementation Method 1
a refill dielectric layer is non-conformally deposited in cut metal gate trenches to create air gaps
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.