Segmented Gate Cap Layout for Contact Isolation in CMOS
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Solution Overview
Problem
In semiconductor devices, particularly in CMOS technology, the formation of seams inside Silicon Nitride caps can lead to electrical shorts between gate contacts and metals above the gate, resulting in increased gate resistance and poor circuit performance, especially as channel lengths shrink below 20 nanometers.
Innovation Solution
A gate structure is designed with a capless third portion between cap-covered portions, where the gate contact is placed on top of the capless portion, preventing electrical shorts and reducing gate resistance by constraining the SiN seams within the cap portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous Silicon Nitride cap is formed over the gate structure, then the gate is isolated from source/drain contacts, but seams form inside the cap creating electrical shorts between gate contact and metals above the gate
Solution Approach 1:
The gate structure is divided into three portions: a first portion with a cap, a second portion with a cap, and a third capless portion in between. This segmentation prevents continuous cap formation and eliminates seam-related electrical shorts while maintaining isolation where needed.
Solution Approach 2:
Different portions of the gate structure have different cap configurations - capped regions provide isolation while the capless region allows direct metal contact without seam interference. This local differentiation optimizes both isolation and electrical connection.
2Productivity
If the gate structure is scaled down to channel lengths below 20 nanometers, then device density increases, but seam formation becomes more prevalent causing increased gate resistance
Solution Approach 1:
By segmenting the gate into capped and capless portions, the invention prevents seam formation that would otherwise be exacerbated by scaling, thereby maintaining low gate resistance while achieving high device density through efficient space utilization.
3Reliability
If a cap is formed over the entire gate structure, then isolation is maximized, but gate contact formation becomes complex due to seam management requirements
Solution Approach 1:
The segmented gate structure with distinct capped and capless portions simplifies gate contact formation by eliminating the need to navigate through seams, while maintaining isolation in the capped regions.
Solution Approach 2:
The cap is extracted or removed from the third portion of the gate structure, creating a capless region that simplifies contact formation by eliminating seam-related complications in that specific area.
Data Source
AI summary
In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.