Segmented Gate Layout for Dense Semiconductor Cell Scaling
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and improved electric characteristics while maintaining reliability and performance, particularly in the increasing complexity and demand for multifunctional devices.
Innovation Solution
The semiconductor device design includes a substrate with multiple active regions, source/drain patterns, channel patterns, gate electrodes, and metal layers, featuring gate cutting patterns that cover the outermost side surfaces of the channel patterns to enhance integration density and electric characteristics, along with a method of fabricating these structures using advanced lithography and epitaxial growth processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complexity and integration density of semiconductor devices are increased to meet demand for high performance and multiple functions, then device functionality and performance are improved, but manufacturing complexity and fabrication difficulty increase
Solution Approach 1:
The gate electrode is divided into multiple gate electrode patterns through gate cutting patterns, allowing independent control and optimization of different transistor regions. This segmentation enables complex device functionality while maintaining manageable fabrication processes by breaking down the gate structure into controllable units.
Solution Approach 2:
Gate cutting patterns are formed at different depth levels within the gate electrode structure, creating a three-dimensional segmented architecture. This dimensional approach allows multiple gate regions to be defined vertically, enabling complex device functionality without proportionally increasing lateral fabrication complexity.
2Area of moving object
If integration density is increased to achieve smaller device size, then device footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Gate cutting patterns are formed in advance during the gate electrode formation process, before final interlayer insulating layer deposition. This preliminary action allows precise definition of gate regions at optimal fabrication stages, reducing the precision burden on subsequent processing steps and enabling higher integration density.
3Productivity
If device size is reduced for higher integration density, then chip area utilization is improved, but electric characteristics and reliability may deteriorate
Solution Approach 1:
Different gate electrode patterns are created with locally optimized characteristics through selective gate cutting. Each gate region can have tailored electrical properties suitable for its specific function, maintaining high reliability even as overall device size is reduced for higher integration density.
Data Source
AI summary
A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.